SLUSC39B June 2015 – February 2017 TPS53647
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 V3R3 LDO
- 7.3.2 PWM Operation
- 7.3.3 Current Sense and IMON Calculation
- 7.3.4 Setting the Load-Line (DROOP)
- 7.3.5 Load Transitions
- 7.3.6 Overshoot Reduction (OSR)
- 7.3.7 Undershoot Reduction (USR)
- 7.3.8 AutoBalance™ Current Sharing
- 7.3.9 Phase Overlap
- 7.3.10 VID
- 7.3.11 PWM and SKIP Signals
- 7.3.12 TSEN (Thermal Sense) Pin
- 7.3.13 RESET Function
- 7.3.14 Input UVLO
- 7.3.15 V5 Pin Undervoltage Lockout (UVLO)
- 7.3.16 Output Undervoltage Protection (UVP)
- 7.3.17 Overvoltage Protection (OVP)
- 7.3.18 Overcurrent Limit (OCL) and Overcurrent Protection (OCP)
- 7.3.19 Over Temperature Protection (OTP)
- 7.3.20 VR_HOT and VR_FAULT Indication
- 7.4 Device Functional Modes
- 7.5
Programming
- 7.5.1
User Selections
- 7.5.1.1 Switching Frequency
- 7.5.1.2 IMAX Information
- 7.5.1.3 Boot Voltage
- 7.5.1.4 Per-Phase Overcurrent Limit (OCL) Level
- 7.5.1.5 Overshoot Reduction (OSR) and Undershoot Reduction (USR) Levels
- 7.5.1.6 Slew Rate Selection
- 7.5.1.7 Mode Selections
- 7.5.1.8 Soft Start Slew Rate and PMBus Addresses
- 7.5.1.9 Ramp Selection
- 7.5.1.10 Maximum Active Phase Numbers
- 7.5.1.11 Pinstrap Mode Settings
- 7.5.1.12 NVM Default Settings
- 7.5.1.13 4-Phase Application
- 7.5.2 Supported Protections and Fault Reports
- 7.5.3 Supported PMBus Address and Commands Summary
- 7.5.1
User Selections
- 7.6
Register Maps
- 7.6.1 PMBus Description
- 7.6.2
PMBus Functionality
- 7.6.2.1 PMBus Address
- 7.6.2.2 Pin Strap Settings
- 7.6.2.3
Supported PMBus Commands
- 7.6.2.3.1 OPERATION (01h)
- 7.6.2.3.2 ON_OFF_CONFIG (02h)
- 7.6.2.3.3 CLEAR_FAULTS (03h)
- 7.6.2.3.4 WRITE_PROTECT (10h)
- 7.6.2.3.5 STORE_DEFAULT_ALL (11h)
- 7.6.2.3.6 RESTORE_DEFAULT_ALL (12h)
- 7.6.2.3.7 CAPABILITY (19h)
- 7.6.2.3.8 VOUT_MODE (20h)
- 7.6.2.3.9 VOUT_COMMAND (21h)
- 7.6.2.3.10 VOUT_MAX (24h)
- 7.6.2.3.11 VOUT_MARGIN_HIGH (25h)
- 7.6.2.3.12 VOUT_MARGIN_LOW (26h)
- 7.6.2.3.13 IOUT_CAL_OFFSET (39h)
- 7.6.2.3.14 VOUT_OV_FAULT_RESPONSE (41h)
- 7.6.2.3.15 VOUT_UV_FAULT_RESPONSE (45h)
- 7.6.2.3.16 IOUT_OC_FAULT_LIMIT (46h)
- 7.6.2.3.17 IOUT_OC_FAULT_RESPONSE (47h)
- 7.6.2.3.18 IOUT_OC_WARN_LIMIT (4Ah)
- 7.6.2.3.19 OT_FAULT_LIMIT (4Fh)
- 7.6.2.3.20 OT_FAULT_RESPONSE (50h)
- 7.6.2.3.21 OT_WARN_LIMIT (51h)
- 7.6.2.3.22 VIN_OV_FAULT_LIMIT (55h)
- 7.6.2.3.23 IIN_OC_FAULT_LIMIT (5Bh)
- 7.6.2.3.24 IIN_OC_FAULT_RESPONSE (5Ch)
- 7.6.2.3.25 IIN_OC_WARN_LIMIT (5Dh)
- 7.6.2.3.26 STATUS_BYTE (78h)
- 7.6.2.3.27 STATUS_WORD (79h)
- 7.6.2.3.28 STATUS_VOUT (7Ah)
- 7.6.2.3.29 STATUS_IOUT (7Bh)
- 7.6.2.3.30 STATUS_INPUT (7Ch)
- 7.6.2.3.31 STATUS_TEMPERATURE (7Dh)
- 7.6.2.3.32 STATUS_CML (7Eh)
- 7.6.2.3.33 STATUS_MFR_SPECIFIC (80h)
- 7.6.2.3.34 READ_VIN (88h)
- 7.6.2.3.35 READ_IIN (89h)
- 7.6.2.3.36 READ_VOUT (8Bh)
- 7.6.2.3.37 READ_IOUT (8Ch)
- 7.6.2.3.38 READ_TEMPERATURE_1 (8Dh)
- 7.6.2.3.39 READ_POUT (96h)
- 7.6.2.3.40 READ_PIN (97h)
- 7.6.2.3.41 PMBus_REVISION (98h)
- 7.6.2.3.42 MFR_ID (99h)
- 7.6.2.3.43 MFR_MODEL (9Ah)
- 7.6.2.3.44 MFR_REVISION (9Bh)
- 7.6.2.3.45 MFR_DATE (9Dh)
- 7.6.2.3.46 MFR_VOUT_MIN (A4h)
- 7.6.2.3.47 MFR_SPECIFIC_00 (Per-Phase Overcurrent Limit) (D0h)
- 7.6.2.3.48 MFR_SPECIFIC_01 (Telemetry Averaging Time) (D1h)
- 7.6.2.3.49 MFR_SPECIFIC_04 (Read VOUT) (D4h)
- 7.6.2.3.50 MFR_SPECIFIC_05 (VOUT Trim) (D5h)
- 7.6.2.3.51 MFR_SPECIFIC_07 (Additional Function Bits) (D7h)
- 7.6.2.3.52 MFR_SPECIFIC_08 (Droop) (D8h)
- 7.6.2.3.53 MFR_SPECIFIC_09 (OSR/USR) (D9h)
- 7.6.2.3.54 MFR_SPECIFIC_10 (Maximum Operating Current) (DAh)
- 7.6.2.3.55 MFR_SPECIFIC_11 (VBOOT) (DBh)
- 7.6.2.3.56 MFR_SPECIFIC_12 (Switching Frequency and TRISE) (DCh)
- 7.6.2.3.57 MFR_SPECIFIC_13 (Slew Rate and Other Operation Modes) (DDh)
- 7.6.2.3.58 MFR_SPECIFIC_14 (Ramp Height) (DEh)
- 7.6.2.3.59 MFR_SPECIFIC_15 (Dynamic Phase Shedding Thresholds) (DFh)
- 7.6.2.3.60 MFR_SPECIFIC_16 (VIN UVLO) (E0h)
- 7.6.2.3.61 MFR_SPECIFIC_20 (Maximum Operational Phase Number) (E4h)
- 7.6.2.3.62 MFR_SPECIFIC_22 ( VOUT_UV_FAULT_threshold) (E6h)
- 7.6.2.3.63 MFR_SPECIFIC_44 (DEVICE_CODE) (FCh)
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Select the Switching Frequency
- 8.2.2.2 Set the Maximum Output Current (IMAX)
- 8.2.2.3 Select the Soft-Start Slew Rate
- 8.2.2.4 Select the Operation Mode
- 8.2.2.5 Choose Inductor
- 8.2.2.6 Select the Per-Phase Valley Current Limit And Ramp Level
- 8.2.2.7 Set the Load-Line
- 8.2.2.8 Set the BOOT Voltage
- 8.2.2.9 Set OSR/USR Thresholds to Improve Load Transient Performance
- 8.2.2.10 Digital Current Monitor (IMON) Gain and Filter Setting
- 8.2.2.11 Compensation Design
- 8.2.2.12 Set PMBus Addresses
- 8.2.2.13 Programming the Device with the PMBus
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
-
10Layout
- 10.1
Layout Guidelines
- 10.1.1 Schematic Review Checklist
- 10.1.2
PCB Design Guidelines
- 10.1.2.1 Layer Stack-up, 8-Layer PCB as example
- 10.1.2.2 Current Sensing Lines
- 10.1.2.3 Feedback Voltage Sensing Lines
- 10.1.2.4 PWM Lines
- 10.1.2.5 Power Chain Symmetry
- 10.1.2.6 Placing Analog Signal Components
- 10.1.2.7 Grounding Recommendations
- 10.1.2.8 TI Smart Power Stage CSD95372BQ5MC
- 10.1.2.9 Power Delivery and Power Density
- 10.2 Layout Example
- 10.1
Layout Guidelines
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
- RTA|40
Thermal pad, mechanical data (Package|Pins)
- RTA|40
Orderable Information
1 Features
- 8-bit Selectable BOOT Voltage via Pinstrap or NVM: 0.5 V to 2.5 V (down to 5-mV Step)
- 1-, 2-, 3-, or 4- Phase Operation
- PMBus™ System Interface for Telemetry of Voltage, Current, Power, Temperature, and Fault Conditions
- 1.8-V and 3.3-V PMBus Bias Compatible
- Fault Reporting: Output Voltage, Output Current, and Temperature
- Configurable with Non-Volatile Memory (NVM) or Resistor Pinstrap
- 16 Levels of Programmable OCP with Pinstrap or NVM
- Fast Transient with DCAP+™Control
- Optimized Efficiency at Light and Heavy Loads
- Support Pre-Bias Startup
- Phase Current Imbalance Detection and Reporting
- 8 Independent Levels of Overshoot Reduction (OSR) and Undershoot Reduction (USR)
- Driverless Configuration for Efficient High-Frequency Switching
- Fully Compatible with CSD95372BQ5MC NexFET™ Power Stage
- Accurate, Adjustable Voltage Positioning
- 300-kHz to 1-MHz Frequency Selections with Closed-loop Frequency Control
- Patented AutoBalance™ Phase Balancing
- Uses TI’s Fusion Digital Power Designer GUI
- Dynamic Phase Shedding with Programmable Current Threshold
- Conversion Voltage Range: 4.5 V to 17 V
- Small, 6 mm × 6 mm, 40-Pin, QFN, PowerPAD™ Package
2 Applications
- Application-Specific Integrated Circuit (ASIC) Power in Communications Equipment
- High Density Power Solutions
- Server Power
- Smart Power Systems
3 Description
The TPS53647 is a high-current, multi-phase, step-down controller. The device offers built-in non volatile memory (NVM) and PMBus interface. It is compatible with the NexFET power stages (CSD95372BQ5MC). The TPS53647 provides 8-bit BOOT voltage selection covering output voltage from 0.5 V to 2.5 V, with steps as small as 5 mV, which is ideal for high current application with accurate output voltage setting. Advanced control features such as D-CAP+ architecture with undershoot reduction (USR) and overshoot reduction (OSR) provide fast transient response, lowest output capacitance, and high efficiency. The TPS53647 also provides novel phase interleaving strategy and dynamic phase shedding for efficiency improvement at light loads. In addition, the TPS53647 supports the PMBus communication interface with systems for telemetry of voltage, current, power, temperature, and fault conditions. Some of the configurations can be programmed by pinstrap or PMBus and stored in non-volatile memory to minimize the external component count.
The TPS53647 is offered in a space saving, thermally enhanced 40-pin QFN package and is rated to operate from –40°C to 125°C.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| TPS53647 | QFN (40) | 6.00 mm × 6.00 mm |
- For all available packages, see the orderable addendum at the end of the datasheet.
Simplified Schematic
