SCES528F December 2003 – May 2017 SN74LVC1G373
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Timing Requirements: TA = -40°C to +85°C
- 6.7 Timing Requirements: TA = -40°C to +125°C
- 6.8 Switching Characteristics: TA = -40°C to +85°C
- 6.9 Switching Characteristics: TA = -40°C to +85°C
- 6.10 Switching Characteristics: TA = -40°C to +125°C
- 6.11 Operating Characteristics
- 6.12 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- DBV|6
- YZP|6
- DCK|6
Thermal pad, mechanical data (Package|Pins)
Orderable Information
1 Features
- Available in the Texas Instruments
NanoFree™ Package - Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Provides Down Translation to VCC
- Max tpd of 4 ns at 3.3 V
- Low Power Consumption: 10-μA
Maximum ICC - ±24-mA Output Drive at 3.3 V
- Ioff Supports Partial-Power-Down Mode and Back Drive Protection
- Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
2 Applications
- Servers
- Printers
- Telecom and Grid Infrastructure
- Memory Addressing
- Buffer Registers
- Electronic Point of Sale
3 Description
The SN74LVC1G373 device is a single D-type latch designed for 1.65-V to 5.5-V VCC operation.
This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs.
NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
OE does not affect the internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
Device Information(1)
| PACKAGE NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74LVC1G373DBV | SOT-23 (6) | 2.90 mm × 1.60 mm |
| SN74LVC1G373DCK | SC70 (6) | 2.00 mm × 1.25 mm |
| SN74LVC1G373YZP | DSBGA (6) | 1.41 mm × 0.91 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Logic Diagram (Positive Logic)
