SCES592I July 2004 – September 2017 SN74AUP1G79
PRODUCTION DATA.
The AUP family is TI's premier solution to the industry's low-power needs in battery-powered portable applications. This family assures a very-low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, thus resulting in an increased battery life. The AUP devices also maintain excellent signal integrity.
The SN74AUP1G79 is a single positive-edge-triggered D-type flip-flop. When data at the data (D) input meets the setup-time requirement, the data is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
The SN74AUP1G79 device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs when the device is powered down. This inhibits current backflow into the device which prevents damage to the device.
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| SN74AUP1G79DBV | SOT-23 (5) | 2.90 mm × 1.60 mm |
| SN74AUP1G79DCK | SC70 (5) | 2.00 mm × 1.25 mm |
| SN74AUP1G79DRL | SOT-5X3 (5) | 1.60 mm × 1.20 mm |
| SN74AUP1G79DRY | SON (6) | 1.45 mm × 1.00 mm |
| SN74AUP1G79DSF | SON (6) | 1.00 mm × 1.00 mm |
| SN74AUP1G79DPW | X2SON (5) | 0.80 mm x 0.80 mm |
| SN74AUP1G79YFP | DSBGA (6) | 1.16 mm × 0.76 mm |
| SN74AUP1G79YZP | DSBGA (5) | 1.39 mm × 0.89 mm |