Design Goals

Design Description

This application brief shows how to implement a voltage window comparator circuit, targeted to monitor a 28-V power rail, a spacecraft bus voltage commonly found in smaller aircraft. This wide single-supply window comparator circuit utilizes a dual open-collector comparator and 3 resistors to set the window voltage. A shunt regulator, TL1431-SP, is used to provide a reference voltage from the input voltage. Therefore, only a single power supply is utilized for the input portion of the circuit. The LM193AQML-SP was used for its open collector output, radiation specifications, and two channel count. Whenever the input voltage, V_in, is within the window of comparison (26 V to 30 V), the output of the circuit, V_OUT, is high. Whenever Vin is outside of the window of comparison, the V_OUT is pulled down to GND.

Design Notes

1. Select a high-voltage comparator with an open collector output stage.
2. Select a comparator with low input offset voltage to optimize accuracy.
3. Calculate values for the resistor divider so that V_OUT goes high whenever V₁ crosses V_REF and goes low whenever V₂ crosses V_REF.
4. Calculate R5 such that shunt regulator is within sink current specification for entire operating range.

Design Steps

1. Select a high-voltage comparator with an open collector output stage that can operate at the highest possible supply voltage. In this design, the highest input/supply voltage is 36 V.
2. Determine an appropriate reference level, V_REF, for the window comparator. The TL1431-SP internal reference voltage, 2.5 V, was used for ease of calculations. If another reference voltage were to be used with the TL1431-SP, a voltage divider would be needed between the cathode and anode of the shunt regulator, with V_REF between the resistors.
3. Calculate the value of R₅, the resistor across V_IN and V_REF, by relating V_REF to the operating voltage range. Ensure that R₅ is at a level where the shunt regulator is sufficiently biased for the entire operating range. The current needed to bias the TL1431-SP, I_Bias, has to be between 1 mA and 100 mA. A 4.7-kΩ resistor was chosen as it kept the bias current within this range for the entire voltage operating range.
   Equation 1. $I_{\mathrm{Bias} \left(\mathrm{Min}\right)}=\frac{V_{\mathrm{in} \left(\mathrm{Min}\right) }- V_{\mathrm{Ref}}}{R_5}=\frac{20V-2.5V}{4.7\mathrm{k\Omega }}=3.72\mathrm{mA}$
   Equation 1. $I_{\mathrm{Bias} \left(\mathrm{Max}\right)}=\frac{V_{\mathrm{in} \left(\mathrm{Max}\right) }- V_{\mathrm{Ref}}}{R_5}=\frac{36V-2.5V}{4.7\mathrm{k\Omega }}=7.12\mathrm{mA}$
   Values between 350 Ω and 16 kΩ could be used in this design. Consideration was made to minimize the bias current, yet give some buffer from the 1 mA minimum specification. If V_REF is seen to be noisy, a decoupling capacitor can be placed between the node and GND to filter out the noise.
4. The positive input to the top comparator, V₁, and the negative input to the bottom comparator, V₂, can be related to V_in through voltage division:
   Equation 1. $V_1 = V_{\mathrm{in}}\left(\frac{R_2+R_3}{R_1+R_2+R_3}\right), V_2 = V_{\mathrm{in}}\left(\frac{R_3}{R_1+R_2+R_3}\right)$

   The window comparator trips when V₁ passes V_REF to output high, and again when V₂ passes V_REF to output low. The comparator is low if V₁ is less than V_REF. In this design, the window comparator will trip high when V_in equals 26 V and trip low when V_in equals 30 V; both while V_REF equals 2.5 V.

   Equation 1. $2.5 = 26\left(\frac{R_2+R_3}{R_1+R_2+R_3}\right) \to 10.4 = \frac{R_1+R_2+R_3}{R_2+R_3}$
   Equation 1. $2.5 = 30\left(\frac{R_3}{R_1+R_2+R_3}\right) \to 12 = \frac{R_1+R_2+R_3}{R_3}$

5. Solve both equations from step 4 for (R₁+R₂+R₃) and substitute one equation for the other.
   Equation 1. $10.4R_2+10.4R_3 = R_1+R_2+R_3$
   Equation 1. $12R_3 = R_1+R_2+R_3$
   Equation 1. $12R_3 = 10.4R_2+10.4R_3$
   Equation 1. $10.4R_2 = 1.6R_3 \to 6.5R_2 = R_3$
6. Using the relationship obtained in step 5, solve for a relationship between R₁ and R₂.
   Equation 1. $12(6.5R_2) = R_1+R_2+6.5R_2$
   Equation 1. $78R_2 = R_1+7.5R_2 \to 70.5R_2 = R_1$
7. Using the equations derived in steps 5 and 6, size resistors R₁, R₂, and R₃ accordingly. For this design, R₂ was set to be 2.55 kΩ, which meant R₁ and R₃ would be 179.775 kΩ and 16.575 kΩ, respectively. The magnitude of these resistors were chosen based off of the current consumption across the voltage divider (around 100 to 180 μA across the operating condition).
8. Select a 5% tolerant resistor to act as the pullup resistor, R₄, from the output of the window comparator to V_PU. Size this component large enough to ensure the current sinked by the comparator is not large, but small enough that the leakage current drawn by the comparator output when high is not causing too large of a voltage drop.
9. The values obtained in step 7 were adjusted for 1% resistor tolerances to be 178 kΩ, 2.55 kΩ, and 16.5 kΩ for R₁, R₂, and R₃, respectively. Due to these changes, the window of comparison was shifted to trip earlier for overvoltage conditions and later for undervoltage conditions. In the DC Simulation Results, the window of comparison is between 25.8595 V and 29.856 V.

Design Simulations

DC Simulation Results

Transient Simulation Results

References:

1. SPICE Simulation File: http://www.ti.com/lit/zip/snom708.

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