1 Features

• 10-MHz to 100-MHz Input Pixel Clock Support
• Single Differential Pair Interconnect
• Programmable Data Payload:
  • 10-bit Payload up to 100 MHz
  • 12-bit Payload up to 75 MHz
• Continuous Low Latency Bidirectional Control Interface Channel With I²C Support at 400 kHz
• 2:1 Multiplexer to Choose Between Two Input Imagers
• Embedded Clock With DC-Balanced Coding to Support AC-Coupled Interconnects
• Capable of Driving up to 25 Meters Shielded Twisted-Pair
• Receive Equalizer Automatically Adapts for Changes in Cable Loss
• Four Dedicated General-Purpose Input/Output Pins (GPIO) Available on Both Serializer and Deserializer
• LOCK Output Reporting Pin and AT-SPEED BIST Diagnosis Feature to Validate Link Integrity
• 1.8-V, 2.8-V or 3.3-V Compatible Parallel Inputs on Serializer
• Single Power Supply at 1.8 V
• ISO 10605 and IEC 61000-4-2 ESD Compliant
• Automotive-Grade Product: AEC-Q100 Grade 2 Qualified
• Temperature Range −40°C to +105°C
• Small Serializer Footprint (5 mm × 5 mm)
• EMI/EMC Mitigation on Deserializer
  • Programmable Spread Spectrum (SSCG) Outputs
  • Receiver Staggered Outputs

2 Applications

• Front- or Rear-View Camera for Collision Mitigation
• Surround View for Parking Assistance

3 Description

The DS90UB91xQ-Q1 chipset offers an FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single differential pair. The DS90UB91xQ-Q1 chipsets incorporate differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer and deserializer pair is targeted for connections between imagers and video processors in an electronic control unit (ECU). This chipset is ideally suited for driving video data that requires up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.

There is a multiplexer at the deserializer to choose between two input imagers. The deserializer can have only one active input imager. The primary video transport converts 10- and 12-bit data over a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I²C port and is independent of video blanking period.

1. For all available packages, see the orderable addendum at the end of the data sheet.

Typical Application Circuit