The TPS7B4255EVM-062 evaluation module contains the TPS7B4255-Q1 LDO with input and output capacitors installed. These three components provide an implementation example, as illustrated by the white boxes in Figure 3-2. The prepopulated capacitors are sized to ensure the minimum capacitance requirements are maintained under all normal operating conditions. Optional pads are available to test the LDO with additional setpoint options, as well as input and output capacitors beyond what is already installed on the EVM.

Setpoint resistors are prepopulated on the TPS7B4255EVM-062 to configure the TPS7B84-Q1 LDO with an output voltage of 3.3 V, 5 V, or 8 V. With a shunt placed across the pins of jumper J11, the output of the TPS7B84-Q1 supplies the ADJ/EN pin of the TPS7B4255-Q1. If a different voltage than the TPS7B84-Q1 output is desired to drive the ADJ/EN pin, remove the shunt from jumper J11 and use a combination of J5, R1, R3, and C10 to configure the ADJ/EN pin to be a function of the input voltage. Alternatively, TP1 can be used to directly drive ADJ/EN with an external voltage source.

The TPS7B84-Q1 LDO can be enabled or disabled by using the J14 3-pin header:

• Place a 2-pin shunt across the header to tie VIN to EN to enable the device
• Place a 2-pin shunt across the header to tie GND to EN to disable the device

Alternatively, by connecting an external function generator to TP2 (EN) and a nearby GND post (J9), the user can enable or disable the TPS7B84-Q1 LDO after VIN is applied. Figure 3-1 illustrates the result of the TPS7B4255EVM-062 during turn-on. Jumper J14 has a shunt to connect EN of the TPS7B84-Q1 to VIN to enable the device for this turn-on plot.

If desired, a current probe can be inserted in the EVM as illustrated in Figure 3-2 to measure the input and output current. The slots were sized to fit most current probes, such as the LeCroy? AP015 or CP031 current probes.

The board layout is designed such that the I_in current probe slot does not detect any current that goes to the TPS7B84-Q1 circuit or its peripherals during start up or during any other operational mode. Thus, the I_in current probe slot can be used to isolate and accurately measure current into the TPS7B4255-Q1 solution.

The user has two options for providing a DC load on the output of the TPS7B4255-Q1. J7 can be used to place a DC load that flows through the current sense path on the output of the LDO. Alternatively, the J4 (VOUT) and J10 (GND) banana connectors can be used for external measurements and loading; however, the IOUT loop does not sense current flowing through these connectors. In cases where very fast transient tests are performed, ringing may occur on VIN or VOUT as a result of the PCB parasitic inductance. Placing a strip of wire on the exposed copper in the current path can reduce this ringing. 10 AWG wire can be used as needed. If ringing persists, install damping networks by adding a series resistor and capacitor in parallel with VIN. Locations where damping can be installed include C1 and R2, and C15 and R20.

Optional kelvin sense points are provided using the SMA connectors J1 (VIN) and J2 (VOUT).