ZHCSEY4 April   2016 DS90UB924-Q1

PRODUCTION DATA.  

1. 1 特性
2. 2 應(yīng)用范圍
3. 3 說明
4. 4 修訂歷史記錄
5. 5 Pin Configuration and Functions
6. 6 Specifications
   1. 6.1  Absolute Maximum Ratings
   2. 6.2  ESD Ratings
   3. 6.3  Recommended Operating Conditions
   4. 6.4  Thermal Information
   5. 6.5  DC Electrical Characteristics
   6. 6.6  AC Electrical Characteristics
   7. 6.7  DC and AC Serial Control Bus Characteristics
   8. 6.8  Timing Requirements for the Serial Control Bus
   9. 6.9  Timing Requirements
   10. 6.10 Typical Characteristics
7. 7 Detailed Description
   1. 7.1 Overview
   2. 7.2 Functional Block Diagram
   3. 7.3 Feature Description
      1. 7.3.1  High-Speed Forward Channel Data Transfer
      2. 7.3.2  Low-Speed Back Channel Data Transfer
      3. 7.3.3  Backward Compatible Mode
      4. 7.3.4  Input Equalization
      5. 7.3.5  Common Mode Filter Pin (CMF)
      6. 7.3.6  Power Down (PDB)
      7. 7.3.7  Video Control Signals
      8. 7.3.8  EMI Reduction Features
         1. 7.3.8.1 LVCMOS VDDIO Option
      9. 7.3.9  Built In Self Test (BIST)
         1. 7.3.9.1 BIST Configuration and Status
            1. 7.3.9.1.1 Sample BIST Sequence
         2. 7.3.9.2 Forward Channel and Back Channel Error Checking
      10. 7.3.10 Internal Pattern Generation
          1. 7.3.10.1 Pattern Options
          2. 7.3.10.2 Color Modes
          3. 7.3.10.3 Video Timing Modes
          4. 7.3.10.4 External Timing
          5. 7.3.10.5 Pattern Inversion
          6. 7.3.10.6 Auto Scrolling
          7. 7.3.10.7 Additional Features
      11. 7.3.11 Serial Link Fault Detect
      12. 7.3.12 Oscillator Output
      13. 7.3.13 Interrupt Pin (INTB / INTB_IN)
      14. 7.3.14 General-Purpose I/O
          1. 7.3.14.1 GPIO[3:0]
          2. 7.3.14.2 GPIO[8:5]
      15. 7.3.15 I2S Audio Interface
          1. 7.3.15.1 I2S Transport Modes
          2. 7.3.15.2 I2S Repeater
          3. 7.3.15.3 I2S Jitter Cleaning
          4. 7.3.15.4 MCLK
      16. 7.3.16 AV Mute Prevention
      17. 7.3.17 OEN Toggling Limitation
   4. 7.4 Device Functional Modes
      1. 7.4.1 Clock and Output Status
      2. 7.4.2 FPD-Link (OpenLDI) Input Frame and Color Bit Mapping Select
      3. 7.4.3 Low Frequency Optimization (LFMODE)
      4. 7.4.4 Mode Select (MODE_SEL)
      5. 7.4.5 Repeater Configuration
         1. 7.4.5.1 Repeater Connections
            1. 7.4.5.1.1 Repeater Fan-Out Electrical Requirements
   5. 7.5 Programming
   6. 7.6 Register Maps
8. 8 Application and Implementation
   1. 8.1 Application Information
   2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
         1. 8.2.2.1 Transmission Media
         2. 8.2.2.2 Display Application
      3. 8.2.3 Application Curves
9. 9 Power Supply Recommendations
   1. 9.1 Power Up Requirements and PDB Pin
   2. 9.2 Analog Power Signal Routing
10. 10Layout
    1. 10.1 Layout Guidelines
       1. 10.1.1 CML Interconnect Guidelines
    2. 10.2 Layout Example
11. 11器件和文檔支持
    1. 11.1 文檔支持
       1. 11.1.1 相關(guān)文檔　
    2. 11.2 社區(qū)資源
    3. 11.3 商標(biāo)
    4. 11.4 靜電放電警告
    5. 11.5 Glossary
12. 12機(jī)械、封裝和可訂購信息