SNLS340E November 2011 – November 2015 DS100KR800
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
1 Features
- Comprehensive Product Family:
- DS125BR820: 8-Channel Repeater
- DS125BR401A: 4x Lane Repeater
- DS125BR111: 1x Lane Repeater
- Transparent Management of 10G-KR (802.3ap) Link Training Protocol
- 65 mW/Channel (Typical) Power Consumption
- Advanced Signal Conditioning Features
- Receive Equalization up to 36 dB at 5 GHz
- Transmit De-emphasis up to –12 dB
- Transmit Voltage Control: 700 mV to 1300 mV
- Programmable Through Pin Selection, EEPROM or SMBus Interface
- Selectable 2.5-V or 3.3-V Supply Voltage
- –40°C to +85°C Operating Temperature Range
- Flow-thru Pinout in Leadless WQFN Package
2 Applications
- Front-Port 40G-CR4/SR4/LR4 Link Extensions
- Backplane 40G-KR4 Link Extensions
Simplified Functional Block Diagram
3 Description
The DS100KR800 device is a high performance repeater designed to support 8-channel (unidirectional), 10G-KR, and other high-speed interface serial protocols up to 10.3 Gbps. The continuous time linear equalizer (CTLE) of the receiver provides a boost of up to 36 dB at 5 GHz (10.3125 Gbps) in each of its eight channels. This equalizer is capable of opening an input eye that is completely closed due to inter symbol interference (ISI) induced by interconnect medium such as long backplanes or cables. The transmitter provides a de-emphasis boost of up to –12 dB and output voltage amplitude control from 700 mV to 1300 mV.
When operating in 10G-KR mode, the DS100KR800 transparently allows the host controller and the end point to optimize the full link and negotiate transmit equalizer coefficients as defined in the 802.3ap standard. This seamless management of the link training protocol ensures system level interoperability with minimum latency.
The programmable settings can be applied through pin settings, SMBus (I2C) protocol or an external EEPROM. When operating in the EEPROM mode, the configuration information is automatically loaded on power-up. This eliminates the need for an external microprocessor or software driver.
Device Information(1)
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| DS100KR800 | WQFN (54) | 10.00 mm × 5.50 mm |
- For all available packages, see the orderable addendum at the end of the data sheet.
Typical Application Block Diagram
