The UCC57132-Q1 device provides an undervoltage lockout threshold of 12V and the UCC57138-Q1 device provides an undervoltage lockout threshold of 8V. The device's hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 1V of typical UVLO hysteresis is expected. There is no significant driver output turnon delay due to the UVLO feature, and 2μs of UVLO delay is expected. The UVLO turn-off delay is also minimized as much as possible. The UVLO delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of the input pins. When exit the UVLO, the EN/FLT is charged by external pull up circuit. The fault clear time is depended on the time constant of the R_FLTC and C_FLTC. After exit the UVLO longer than the fault clear time the OUT follow the IN after the first raising edge of the IN.

Figure 7-2 UVLO Timing Diagram