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ZHCSDI3A September 2014 – March 2015 UCC29950

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

D|16
- MPDS178G

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Supply Voltage	VCC	–0.3	20	V
Continuous Input Voltage Range	LLC_CS	–0.3	4.5	V
	FB, AC1, AC2, VBULK, MD_SEL/PS_ON	–0.3	VCC+0.3	V
	AC_DET	0	4.5	V
	SUFS	–0.3	20	V
	SUFG	–0.3	SUFS+0.3	V
	GD1, GD2, PFC_GD	–0.5	VCC+0.5	V
	PFC_CS	–1.3	4.5	V
Continuous Input Current Range	PFC_CS		±15	mA
T_SOL	Lead temperature (10 s)		260	°C
Operational Junction Temperature, T_J		–40	125	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 Storage Conditions

		MIN	MAX	UNIT
T_stg	Storage temperature range	–40	150	°C

6.3 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM is possible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM is possible with the necessary precautions.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
VCC	Supply voltage range	11		18	V
V_FB	FB pin voltage range	0		VCC	V
V_{MD_SEL/PS_ON}	MD_SEL/PS_ON pin voltage range	0		VCC	V
RL1/RL2	Line sensing resistors		9.3		MΩ

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		UCC29950	UNIT
		SOIC (D)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	78.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	40.3
R_θJB	Junction-to-board thermal resistance	36.3
ψ_JT	Junction-to-top characterization parameter	8.9
ψ_JB	Junction-to-board characterization parameter	36.0

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.6 Electrical Characteristics

–40°C < T_J < 125°C⁽⁵⁾, VCC = 12 V, all voltages are with respect to AGND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC Bias Supply (Self Bias Mode)
I_SUFS	Charging current into V_CC	SUFS = 7.5 V, VCC = 4 V	–1	–2	–4	mA
VCC_SB(start)	In Self Bias mode, the controller will not start PFC and LLC gate drive outputs until the start up FET has charged the capacitance on the VCC pin above this level	MD_SEL/PS_ON = VCC at power-up (self bias mode)	15.0	16.2	17.4	V
VCC_{SB_UVLO(stop)}	In Self Bias mode, VCC must be greater than this level to allow the controller to continue to output the PFC and LLC gate drives.	VCC falling Self Bias Mode	7.3	7.9	8.5
VCC Bias Supply (Aux Bias Mode)
VCC_START⁽¹⁾	Controller logic starts at this VCC voltage	VCC rising	4.4	6	7.0	V
VCC_STOP⁽¹⁾	Controller logic stops at this VCC voltage	VCC falling	3.7	5.0	5.8
VCC_{AB_UVLO(start)}	In Aux Bias Mode, VCC must be greater than this level to allow the controller to start the PFC and LLC gate drive outputs.	VCC rising MD_SEL/PS_ON = 0 V at power-up (Aux Bias Mode)	10.0	10.5	10.9
VCC_{AB_UVLO(stop)}	In Aux Bias Mode, VCC must be greater than this level to allow the controller to continue to output the PFC and LLC gate drives.	VCC falling Aux Bias Mode	9.1	9.6	10.0
VCC Supply Current
ICC_ENABLE	Device is Enabled and providing PFC & LLC gate drive outputs	GD1, GD2 at LLC_FMAX. PFC_GD at f_PFC (100 kHz nom). GD1, GD2 and PFC_GD pins unloaded.	7.5	8.0	18.3	mA
MD_SEL/PS_ON, Mode Select Function at Power Up
V_{MODE_SELSB}	Minimum voltage on the MD_SEL/PS_ON pin that will select Self Bias mode on power up (see Device Functional Modes).		1.1	1.6	2.1	V
T_{MODE_SEL_READ}	After VCC pin exceeds VCC_START. This is the minimum time that the MD_SEL/PS_ON pin must remain below V_{MODE_SELSB} to ensure that Aux Bias Mode is selected (see Device Functional Modes).		10			ms
MD_SEL/PS_ON, Power Supply On Function, Aux Bias Mode Only
V_{PS_ONPFC_RUN}	Minimum voltage on the MD_SEL/PS_ON pin that causes PFC stage to run⁽²⁾		20	25	33	%VCC
V_{PS_ONLLCPFC_RUN}	Minimum voltage on the MD_SEL/PS_ON pin that causes PFC and LLC stages to run⁽²⁾		66	75	85	%VCC
AC_DET
V_{OH_TP_LZ}	AC_DET output high	I_{(AC_DET)} = –1 mA	2.5	3.1	4.1	V
V_OL	AC_DET output low	I_{(AC_DET)} = 1 mA	19	35	80	mV
I_{O(max_source)}	AC_DET source current	V_OUT > 2.4 V			–1.6	mA
I_{O(max_sink)}	AC_DET sink current	V_OUT< 0.5 V			6.0	mA
VBULK, PFC OUTPUT VOLTAGE
V_BULK(ovp)	PFC output overvoltage protection (auto recovery)		1.06	1.10	1.14	V
V_BULK(reg)	V_BULK regulation set-point		0.907	0.940	0.973	V
V_{BULK(llc_start)}	LLC operation start threshold		0.70	0.73	0.77	V
V_{BULK(llc_stop)}	LLC operation stop threshold		0.45	0.49	0.53	V
AC1, AC2, AC LINE SENSING FOR PFC
R_AC1	AC1 pin resistance to AGND	AC1 pin	45	60	71	kΩ
R_AC2	AC2 pin resistance to AGND	AC2 pin	45	60	71	kΩ
I_AC(det)⁽³⁾⁽⁷⁾	AC_DET is active HIGH when I_AC is below this level	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	7.03	7.48	7.93	µA_RMS
I_{AC(low_falling)}⁽³⁾⁽⁷⁾	PFC stage stops 100 ms after I_AC is at or below this level	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	7.03	7.48	7.93
I_{AC(low_rising)}⁽³⁾⁽⁷⁾	PFC stage is allowed to start when I_AC is at or above this level	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	8.04	8.55	9.1
I_{AC(high_falling)}⁽³⁾⁽⁷⁾	PFC stage restarts if I_AC falls below this level. No soft-start	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	30.7	32.0	33.3
I_{AC(high_rising)}⁽³⁾⁽⁷⁾	PFC stage stops if I_AC is at or above this level	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	31.8	33.1	34.4
I_AC(halt)⁽³⁾⁽⁷⁾	PFC and LLC stages stop if I_AC is at or above this level	Force current into AC1 or AC2 pins. Unused pin input at 0 V.	32.8	34.2	35.6
PFC_CS, PFC CURRENT SENSE
V_{PFCCS(cav_max)}	Maximum voltage at PFC_CS pin, (ignoring signal ripple due to inductor ripple current) that determines maximum power delivered. Used to determine R_{CS_PFC}. (see PFC Stage Current SensingFigure 13 and Figure 6)		–200	–225	–250	mV
V_PFCCS(max)	Maximum voltage at PFC_CS pin	VBULK pin = 800 mV, \|V_AC1 – V_AC2\| = V_{AC_PEAK}⁽⁴⁾	–570	–800	–950	mV
PFC_GD, PFC GATE DRIVER
V_{HI(pfc_2mA)}	PFC_GD high level	I_{O(PFC_GD)} = –2 mA	11.5	11.8	12.0	V
V_{HI(pfc_75mA)}	PFC_GD high level	I_{O(PFC_GD)} = –75 mA	8.5	9.5	10.5	V
R_{PFC(gd_hi)}	PFC_GD pull-up resistance	I_{O(PFC_GD)} = –50 mA		14	25	Ω
R_{PFC(gd_lo)}	PFC_GD pull-down resistance	I_{O(PFC_GD)} = 75 mA		4.4	10	Ω
t_R(pfc)	PFC_GD rise time	Capacitive load of 1.0 nF on PFC_GD pin, 20% to 80%		30	45	ns
t_F(pfc)	PFC_GD fall time	Capacitive load of 1.0 nF on PFC_GD pin, 20% to 80%		10	25	ns
f_PFC	Switching frequency	Includes dithering of ±2 kHz at nominal 333-Hz rate.	87	98	109	kHz
FB, LLC Control Loop Feedback
V_FB(min)⁽⁸⁾	Minimum voltage on FB pin where LLC frequency is modulated	Below V_{FB_MIN}, LLC frequency is LLC_Fmin	0.17	0.2	0.23	V
V_FB(max)⁽⁸⁾	Maximum voltage on FB pin where LLC frequency is modulated	Between V_{FB_MAX}, and V_{FB_LLC_OFF} LLC frequency is LLC_Fmax	2.90	3	3.10
V_{FB(llc_off)}⁽⁸⁾	Voltage on FB pin above which LLC gate drive terminated	Once V_FB exceeds V_{FB_LLC_OFF}, V_FB must fall below V_{FB_MAX} to resume switching	3.62	3.75	3.88
LLC_FMIN⁽⁸⁾	Minimum LLC switching frequency		63.7	70	74.8	kHz
LLC_FMAX⁽⁸⁾	Maximum LLC switching frequency		321	350	378	kHz
LLC_T(dead)⁽⁹⁾	Time for which GD1 and GD2 are both low during LLC operation at LLC_FMIN	LLC dead-time at minimum switching frequency.	224	300	388	ns
R_FB	Internal resistance from FB pin to AGND		45	60	71	kΩ
LLC_CS, LLC Current Sense
V_CS(ocp3)⁽¹⁰⁾	LLC Overcurrent threshold level three	If this level is exceeded the PFC and LLC stages will stop for t_LONG(fault). Restart with a normal soft-start sequence	0.87	0.9	0.94	V
V_{CS(llc_max)}	Voltage at LLC_CS pin at 100% of full load		0.27	0.30	0.33	V
FAULT Section
t_LONG(fault)	Recovery time after long fault		0.9	1.0	1.5	s
t_SHORT(fault)	Recovery time after short fault		90	100	150	ms
GD1, GD2, LLC GATE Drive Output
V_{GD(hi_2mA)}	GD1, GD2 output high level	I_O(GDx) = –2 mA	11.5	11.8	12	V
V_{GD(hi_75mA)}	GD1, GD2 output high level	I_O(GDx) = –75 mA	9.3	10.1	10.9	V
R_GD(hi)	GD1, GD2 gate driver pull-up resistance	I_O(GDx) = –50 mA		5.8	10.5	Ω
R_GD(lo)	GD1, GD2 gate driver pull-down resistance	I_O(GDx) = 75 mA		1.6	5	Ω
t_r(llcgd)	LLC gate driver rise time	Capacitive load of 1 nF on GD1, GD2 pins		12	30	ns
t_f(llcgd)	LLC gate driver fall time	capacitive load of 1 nF on GD1, GD2 pins (20% to 80%)		11	25	ns
Thermal Shutdown
T_SD	Thermal shutdown temperature				125	°C
T_ST	Start / restart temperature			113		°C

(1) VCC_STARTis always greater than VCC_STOP.

(2) Threshold voltage will track VCC and is therefore specified as a percentage of VCC.

(3) These are specified at 25°C. The relative levels for these specifications track each other. The equivalent line voltages are given in Table 3, assuming a source impedance of 9.3 MΩ.

(4) Tested at peak of line voltage or 90° from zero crossing.

(5) The device has been characterized over the entire temperature range during development. Individual devices may enter temperature shutdown (T_SD) at T_J lower than 125°C.

(6) The device has been characterized over the entire temperature range during development. Individual devices may enter temperature shutdown (T_SD) at T_J lower than 125°C.

(7) This is the current into the AC1 or AC2 pins.

(8) Refer to Figure 1.

(9) Refer to Figure 2.

(10) Refer to Table 4 for other LLC Stage Over-Current Protection Levels.