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ZHCSBT0D November 2013 – July 2016 UCC28180

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

D|8
- MSOI002K

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings⁽¹⁾

Over operating free-air temperature range, all voltages are with respect to GND (unless otherwise noted). Currents are positive into and negative out of the specified terminal.

		MIN	MAX	UNIT
Input voltage range	VCC, GATE	–0.3	22	V
	FREQ, VSENSE, VCOMP, ICOMP	–0.3	7
	ISENSE	–24	7
Input current range	VSENSE, ISENSE	–1	1	mA
Junction temperature, T_J	Operating	–55	150	°C
Lead temperature, T_SOL	Soldering, 10 s		300	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other condition beyond those included under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods of time may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VCC input voltage from a low-impedance source	VCC_OFF + 1V	21	V
Operating junction temperature, T_J	–40	125	°C
Operating frequency	18	250	kHz

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC28180	UNIT
		D
		8 PINS
R_θJA	Junction-to-ambient thermal resistance⁽²⁾	116.1	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance⁽³⁾	62.2
R_θJB	Junction-to-board thermal resistance⁽⁴⁾	56.4
ψ_JT	Junction-to-top characterization parameter⁽⁵⁾	14.4
ψ_JB	Junction-to-board characterization parameter⁽⁶⁾	55.9

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).

(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(5) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(6) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics

Unless otherwise noted, VCC=15Vdc, 0.1µF from VCC to GND, –40°C ≤ T_J = T_A ≤ +125°C. All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC BIAS SUPPLY
ICC_PRESTART	ICC Pre-start current	VCC = VCC_OFF – 0.2 V			75	µA
ICC_STBY	ICC Standby current	VSENSE = 0.5 V	1.8	2.4	3.47	mA
ICC_{ON_load}	ICC Operating current	VSENSE = 4.0 V, C_GATE = 4.7 nF	5.8	7	8.8	mA
UNDER VOLTAGE LOCKOUT (UVLO)
VCC_ON	VCC Turn on threshold		10.8	11.5	12.1	V
VCC_OFF	VCC Turn off threshold		9.1	9.5	10.3	V
	UVLO Hysteresis		1.6	1.7	2	V
VARIABLE FREQUENCY
f_SW	Minimum switching frequency	R_FREQ = 130 kΩ	16.3	18	19.8	kHz
	Typical switching frequency	R_FREQ = 32.7 kΩ	61.75	65	68.25	kHz
	Maximum switching frequency	R_FREQ = 8.2 kΩ	225	250	275	kHz
V_FREQ	Voltage at FREQ pin	T_A = 25°C	1.43	1.5	1.56	V
PWM
D_MIN	Minimum duty cycle	VSENSE = 5.1 V, ISENSE = –0.25 V			0%
D_MAX	Maximum duty cycle	VSENSE = 4.0 V, R_FREQ = 32.7 Ω	94.8%	96.5%	98%
t_OFF(min)	Minimum off time	VSENSE = 3 V, I_COMP = 0.72 V	450	570	690	ns
SYSTEM PROTECTION
V_SOC	ISENSE threshold, soft over current (SOC)		–0.259	–0.285	–0.312	V
V_PCL	ISENSE threshold, peak current limit (PCL)		–0.345	–0.4	–0.438	V
I_ISOP	ISENSE bias current, ISENSE open-pin protection (ISOP)	ISENSE = 0 V		–2.3	–2.95	µA
V_ISOP	ISENSE threshold, ISENSE open-pin protection (ISOP)	ISENSE = open pin		0.085	0.14	V
V_OLP	VSENSE threshold, open loop protection (OLP)	ICOMP = 1 V, ISENSE = 0 V	15.6	16.5	17.6	%V_REF
	Open loop protection (OLP) Internal pull-down current	VSENSE = 0.5 V		100	325	nA
V_UVD	VSENSE threshold, output under-voltage detection (UVD) used for enhanced dynamic response⁽¹⁾		93.25	95	97	%V_REF
V_OVD	VSENSE threshold, output over-voltage detection (OVD) used for Enhanced dynamic response⁽¹⁾		103	105	106.75	%V_REF
V_{OVP_L}	Output over-voltage protection low threshold, VCOMP is discharged by a 4kΩ resistor when VSENSE > V_{OVP_L}		105	107	109	%V_REF
V_{OVP_H}	Output over-voltage protection high threshold, PWM shuts off when VSENSE > V_{OVP_H}		107	109	111	%V_REF
V_{OVP_H(RST)}	Output over-voltage protection (VOVP_H) reset threshold, PWM turns on when VSENSE < V_{OVP_H(RST)}		100	102	104	%V_REF
	ICOMP threshold, external overload protection			0.2	0.25	%V_REF
CURRENT LOOP
g_mi	Transconductance gain		0.75	0.95	1.1	mS
	Output linear range ⁽¹⁾			±50		µA
	ICOMP voltage during OLP	VSENSE = 0 V	2.7	3	3.3	V
VOLTAGE LOOP
V_REF	Reference voltage	T_A = 25°C	4.93	5	5.07	V
		–40°C ≤ T_A ≤ +125°C	4.87	5	5.15	V
g_mv	Transconductance gain without EDR		–40	–56	–70	µS
g_mv-EDR	Transconductance gain under EDR		–230	–280	–340	µS
	Maximum sink current under normal operation	VSENSE = 5 V, VCOMP = 4 V	23	40	57	µA
	Source current under soft start	VSENSE = 4 V, VCOMP = 4 V	–29	–40	–52	µA
	Maximum current under EDR operation	VSENSE = 4 V, VCOMP = 2.5 V		–200	–275	µA
	VSENSE input bias current	VSENSE = 5 V	20	100	250	nA
	VCOMP voltage during OLP	VSENSE = 0.5 V, I_VCOMP= 0.5 mA	0	0.04	0.10	V
	VCOMP rapid discharge current	VCOMP = 2 V, VCC = floating		0.37		mA
V_PRECHARGE	VCOMP precharge voltage	I_VCOMP = –100 µA, VSENSE = 4 V		1.5		V
I_PRECHARGE	VCOMP precharge current	VCOMP = 0 V		–1		mA
	VSENSE threshold, end-of-soft-start	Initial Start-up		98		%V_REF
GATE DRIVER
	GATE current, peak, sinking⁽¹⁾	C_GATE= 4.7 nF		2		A
	GATE current, peak, sourcing⁽¹⁾	C_GATE = 4.7 nF		–1.5		A
	GATE rise time	C_GATE = 4.7 nF, GATE = 2 V to 8 V	8	40	60	ns
	GATE fall time	C_GATE = 4.7 nF, GATE = 8 V to 2 V	8	25	40	ns
	GATE low voltage, no load	I_GATE = 0 A		0	0.01	V
	GATE low voltage, sinking	I_GATE = 20 mA		0.04	0.06	V
	GATE low voltage, sourcing	I_GATE = -20 mA		–0.04	–0.06	V
	GATE low voltage, sinking, OFF	VCC = 5 V, I_GATE = 5 mA	0.1	0.2	0.31	V
	GATE low voltage, sinking, OFF	VCC = 5 V, I_GATE = 20 mA	0.4	0.8	1.4	V
	GATE high voltage	VCC = 20 V, C_GATE = 4.7 nF	14.5	15.2	16.1	V
	GATE high voltage	VCC = 12.2 V, C_GATE = 4.7 nF	10.8	11.2	12	V
	GATE high voltage	VCC = VCC_OFF + 0.2 V, C_GATE = 4.7 nF	8.2	9	10.1	V