ZHCS779C March 2012 – July 2025 UCC28070 , UCC28070A
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
-
6 Detailed Description
- 6.1 Overview
- 6.2 Functional Block Diagram
- 6.3
Feature Description
- 6.3.1 Interleaving
- 6.3.2 Programming the PWM Frequency and Maximum Duty-Cycle Clamp
- 6.3.3 Frequency Dithering (Magnitude and Rate)
- 6.3.4 External Clock Synchronization
- 6.3.5 Multi-phase Operation
- 6.3.6 VSENSE and VINAC Resistor Configuration
- 6.3.7 VSENSE and VINAC Open-Circuit Protection
- 6.3.8 Current Synthesizer
- 6.3.9 Programmable Peak Current Limit
- 6.3.10 Linear Multiplier and Quantized Voltage Feed Forward
- 6.3.11 Enhanced Transient Response (VA Slew-Rate Correction)
- 6.3.12 Bias Voltages (VCC and VREF)
- 6.3.13 PFC Enable and Disable
- 6.3.14 Adaptive Soft-Start
- 6.3.15 PFC Start-Up Hold Off
- 6.3.16 Output Overvoltage Protection (OVP)
- 6.3.17 Zero-Power Detection
- 6.3.18 Thermal Shutdown
- 6.3.19 Current Loop Compensation
- 6.3.20 Voltage Loop Compensation
- 6.4 Device Functional Modes
-
7 Application and Implementation
- 7.1 Application Information
- 7.2
Typical Application
- 7.2.1 Design Requirements
- 7.2.2
Detailed Design Procedure
- 7.2.2.1 Output Current Calculation
- 7.2.2.2 Bridge Rectifier
- 7.2.2.3 PFC Inductor (L1 and L2)
- 7.2.2.4 PFC MOSFETs (M1 and M2)
- 7.2.2.5 PFC Diode
- 7.2.2.6 PFC Output Capacitor
- 7.2.2.7 Current-Loop Feedback Configuration (Sizing of the Current-Transformer Turns-Ratio NCT and Current-Sense Resistor RS)
- 7.2.2.8 Current-Sense Offset and PWM Ramp for Improved Noise Immunity
- 7.2.3 Application Curves
- 7.3 Power Supply Recommendations
- 7.4 Layout
- 8 器件和文檔支持
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
6.3.4 External Clock Synchronization
The UCC28070A has also been designed to be easily synchronized to almost any external frequency source. By disabling frequency dithering (pulling CDR > 5V), the SYNC circuitry is enabled permitting the internal oscillator to be synchronized with pulses presented on the RDM pin. To ensure that a precise 180° phase shift is maintained between the GDA and GDB outputs, the frequency (fSYNC) of the pulses presented at the RDM pin must be at twice the desired fPWM. For example, if a PWM switching frequency of 100kHz is desired, the fSYNC must be 200kHz.
To ensure the internal oscillator does not interfere with the SYNC function, RRT must be sized to set the internal oscillator frequency about 10% below the minimum expected fSYNC.
It must be noted that the PWM modulator gain is reduced by a factor equivalent to the scaled RRT due to a direct correlation between the PWM ramp current and RRT. Adjustments to the current-loop gains must be made accordingly, using the kSYNC factor as indicated in Current Loop Compensation.
It must also be noted that the maximum duty-cycle clamp programmability is affected during external synchronization. The internal timing circuitry responsible for setting the maximum duty cycle is initiated on the falling edge of the synchronization pulse. Therefore, the selection of RDMX becomes dependent on the synchronization pulse width (tSYNC). In this context, tSYNC is a pulse width; tSYNC is not the inverse of fSYNC.
(For use in RDMX
equation immediately below.)
Consequently to minimize the impact of the tSYNC it is clearly advantageous to use the smallest synchronization pulse width feasible (see Electrical Characteristics Table for minimum allowable pulse width).
When external synchronization is used, a propagation delay of approximately 50ns to 100ns exists between internal timing circuits and the falling edge of the SYNC signal, which may result in reduced OFF-time at the highest of switching frequencies. Therefore, at high SYNC frequencies RDMX value must be adjusted downward slightly by (tSYNC – 0.1μs) / tSYNC to compensate. At lower SYNC frequencies, this delay becomes an insignificant fraction of the PWM period, and can be neglected.
The oscillator in the UCC28070A device is not designed to accommodate wide variations in the external SYNC frequency. Do not allow the SYNC frequency variation to exceed ±10% of the nominal fSYNC as used in Equation 8. Excessive variation of fSYNC can cause malfunction of the controller to occur. RRT value must be calculated at the lowest fSYNC.