ZHCS096C February 2011 – July 2024 UCC27200A , UCC27201A
PRODUCTION DATA
- 1
- 1 特性
- 2 應用
- 3 說明
- 4 Pin Configuration and Functions
- 5 Specifications
- 6 Detailed Description
- 7 Application and Implementation
- 8 Power Supply Recommendations
- 9 Layout
- 10Device and Documentation Support
- 11Revision History
- 12Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
訂購信息
4 Pin Configuration and Functions
Figure 4-1 D Package8-Pin SOICTop View
Figure 4-3 DRM Package8-Pin VSONTop View
Figure 4-5 DPR Package10-Pin WSONTop View
Figure 4-2 DDA Package8-Pin SOIC With Exposed PowerPADTop
View
Figure 4-4 DRC Package9-Pin VSONTop ViewTable 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | |||
|---|---|---|---|---|---|
| NAME | DRM/D/DDA | DRC | DPR | ||
| VDD | 1 | 1 | 1 | I | Positive supply to the lower gate driver. De-couple this pin to VSS (GND). Typical decoupling capacitor range is 0.22μF to 1.0μF. |
| HB | 2 | 2 | 2 | I | High-side bootstrap supply. The bootstrap diode is on-chip but the external bootstrap capacitor is required. Connect positive side of the bootstrap capacitor to this pin. Typical range of HB bypass capacitor is 0.022μF to 0.1μF, the value is dependant on the gate charge of the high-side MOSFET however. |
| HO | 3 | 3 | 3 | O | High-side output. Connect to the gate of the high-side power MOSFET. |
| HS | 4 | 4 | 4 | I | High-side source connection. Connect to source of high-side power MOSFET. Connect negative side of bootstrap capacitor to this pin. |
| HI | 5 | 6 | 7 | I | High-side input. |
| LI | 6 | 7 | 8 | I | Low-side input. |
| VSS | 7 | 8 | 9 | O | Negative supply terminal for the device which is generally grounded. |
| LO | 8 | 9 | 10 | O | Low-side output. Connect to the gate of the low-side power MOSFET. |
| N/C | — | 5 | 5/6 | — | No connection. Pins labeled N/C have no connection. |
| PowerPAD(1) | — | — | — | — | Electrically referenced to VSS (GND). Connect to a large thermal mass trace or GND plane to dramatically improve thermal performance. |
(1) Pin VSS and the exposed thermal die pad are internally
connected on the DRC package only. The thermal pad is not directly connected to
any leads of the package on the DDA, DRM and DPR packages; however, it is
electrically and thermally connected to the substrate which is the ground of the
device.