ZHCSC40E February 2014 – May 2018 TPS92630-Q1
PRODUCTION DATA.
- 1 特性
- 2 應用
- 3 說明
- 4 修訂歷史記錄
- 5 說明 （續）
- 6 Pin Configuration and Functions
- 7 Specifications
- 8 Parameter Measurement Information
- 9 Detailed Description
- 10Applications and Implementation
- 11Power Supply Recommendations
- 12Layout
- 13器件和文檔支持
- 14機械、封裝和可訂購信息
9.3.3 FAULT Diagnostics
The TPS92630-Q1 device has two fault pins, FAULT and FAULT_S. FAULT_S is a dedicated fault pin for single-LED short failure and FAULT is for general faults, that is, short, open, and thermal shutdown. The dual pins allow maximum flexibility based on all requirements and application conditions.
The device fault pins can be connected to an MCU for fault reporting. Both fault pins are open-drain transistors with a weak internal pullup. See Figure 19.
In case there is no MCU, one can connect up to 15 TPS92630-Q1 FAULT and FAULT_S pins together. When one or more devices have errors, the respective FAULT? pins go low, pulling the connected FAULT bus down and shutting down all device outputs. Figure 19 shows the fault-line bus connection.
Figure 19. Fault-Line Bus Connection The device releases the FAULT bus when external circuitry pulls the FAULT pin high, on toggling of the EN pin, or on a power cycle of the device. In case there is no MCU, only a power cycle clears the fault. See Figure 20.
Figure 20. Detailed Timing Diagram The following faults result in the FAULT or FAULT_S pin going low: thermal shutdown, open load, output short circuit, single LED short, and REF open or shorted. For thermal shutdown or LED open, release of the FAULT pin occurs when the thermal-shutdown or LED-open condition no longer exists. For other faults, the FAULT and FAULT_S pins stay low even if the condition does not exist. Clearing the faults requires a power cycle of the device.