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SLUSCZ1 May 2017 TPS92518-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

PWP|24
- MPDS372A

散熱焊盤機械數據 (封裝 | 引腳)

PWP|24
- PPTD111R

訂購信息

6.5 Electrical Characteristics

V_VIN = 14 V, -40 °C ≤ T_J ≤ 150 °C, unless otherwise specified

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCCx, VIN
V_CCx	VCCx Voltage	V_VIN = 40 V or V_VIN = 65 V, 0 A ≤ External Load ≤ 500 µA	6.9	7.5	8.25	V
V_CCx2	VCCx Voltage with External Load	External Load = 500 µA	6.9	7.5	8.25	V
V_{CCx_UVLO}	VCCx undervoltage lockout	Falling threshold, V_VIN = 10 V	5.65	5.9	6.1	V
V_{CCx_UVHYS}	VCCx undervoltage lockout Hysteresis			0.25		V
I_VCCx-LIM	VCCx regulator current limit	V_CC shorted to GND.	25	38	48	mA
I_VIN	Operating Current	Not Switching		3	4	mA
V_DO	LDO drop-out voltage	I_VCC = 5 mA, V_VIN = 5 V		90	225	mV
Peak Current Comparator (CSPx, CSNx)
V_CSTx	V_CSPx-V_CSNxpeak current threshold	LEDx_PKTH_DAC = 255	245	255	265	mV
		LEDx_PKTH_DAC = 127	118.5	127	135.5	mV
		LEDx_PKTH_DAC = 10		10		mV
I_CSN	CSN input bias current			0.4	1.5	µA
t_DEL	CSN pin falling delay	CSNx fall to GATEx fall (1V/us stimulus)		58	110	ns
t_LEB	Leading edge blanking (minimum on-time)	Minimum Pulse Width	165	200	235	ns
CSP_UVLO	CSPx UVLO Falling Threshold		4.65	4.90	5.15	V
CSP_UVLO-H	CSPx UVLO Hysteresis			520		mV
Gate Drivers (GATEx, SWx and BOOTx)
R_DSP	GATEx PFET ( R_{DS High})			7.3		Ω
R_DSN	GATEx NFET ( R_{DS Low})			2.8		Ω
V_BOOT-UVLO	Voltage where gate drive is disabled	V_BOOT to V_SW , V_BOOT falling	3.6	4.4	5.2	V
V_{BOOT-UVLO-HYS}	Hysteresis on BOOTx UVLO	V_BOOTxto V_SWx		200		mV
I_{PD PWMx}	Pull down from SWx when PWMx Low	PWMx low, (BOOTx to SWx) = 5V, V_SWx= 8V		200	260	µA
I_{PD BOOTx}	V_BOOTx -V_SWx< V_BOOT-UVLO	PWMx high, (BOOTx to SWx) < BOOT_UVLO, V_SWx = 8 V		5	7	mA
I_{BOOT_Q}	BOOTx quiescent current	(BOOTx to SWx) = 5.5 V, 0 V ≤ V_SWx ≤ 65 V		100	200	µA
OFF-TIMER
t_OFF	Off-time	V_LEDx = 30 V, t_OFFXDAC = 255	3.2	4.1	4.8	µs
t_D-OFF	COFF threshold to gate rising delay	Specified by design		50		ns
t_OFF-MAX	Maximum off-time	t_OFF-MAXDAC = 255		65		µs
Enable and Input UVLO
V_EN/UV1	EN/UV pin threshold	EN/UV pin rising	1.18	1.24	1.30	V
V_EN/UV-HYS1	EN/UV pin hysteresis	Difference between rising and falling threshold		100		mV
t_EN/UV1	EN/UV pin delay	EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0		300		ns
t_EN/UV1	EN/UV pin delay	EN/UV pin falling to GATEx pin falling		470		ns
I_EN/UV-HYST1	EN/UV Hysteresis Current	EN/UV = 2 V	12	16	28	µA
V_EN/UV2	EN/UV LED1_EN and LED2_EN override threshold	EN/UV pin rising writes LED1_EN and LED2_EN = 1		23.4		V
V_EN/UV-HYS2	EN/UV pin hysteresis	Difference between rising and falling threshold		3		V
t_EN/UV2	EN/UV pin delay 2	EN/UV pin rising to GATEx pin rising. LEDx_MAXOFF_DAC = 0		520		ns
PWM, MOSI, SCK, SSN
I_LKG	Leakage current				1	µA
V_IL	Low level input voltage threshold		0.8			V
V_IH	High level input voltage threshold				1.8	V
t_PWM	PWM pin delay	PWM pin rising to GATE pin rising		68	105	ns
t_PWM	PWM pin delay	PWM pin falling to GATE pin falling		55	100	ns
MISO
V_OL	MISO low, I_MISOapplied	I_MISO = 10 mA		0.26	0.51	V
R_DS	MISO Pull-down resistance	I_MISO = 10 mA		26		Ω
ADC
ADC_TEMP	ADC Reading T = –40°C			104		Code
	ADC Reading T = 25°C			130		Code
	ADC Reading T= 150°C			171		Code
ADC_LEDx	ADC Reading V_LEDx= 60 V		226	230	240	Code
	ADC Reading V_LEDx = 10 V		37	38	39	Code
	ADC Reading V_LEDx = 1 V		2	3	4	Code
SPI Interface
t_{SS_SU}	SSN Setup Time	Falling edge of SSN to 1st SCK rising edge	500			ns
t_{SS_H}	SSN Hold Time	Falling edge of 16th SCK to SSN rising edge	250			ns
t_SCK	SCK Period	Clock period	500			ns
D_SCK	SCK Duty Cycle	Clock duty cycle	40		60	%
t_SU	MOSI Setup Time	MOSI valid to rising edge SCK	250			ns
t_H	MOSI Hold Time	MOSI valid after rising edge SCK	275			ns
t_{HI_Z}	MISO Tri-State Time	Time to tri-state (deactivate low-side switch) MISO after SSN rising edge	110		320	ns
t_{MISO_HL}	MISO Valid High-to-Low	Time to place valid "0" on MISO after falling SCK edge			320	ns
t_{MISO_LH}	MISO Valid Low-to-High	Time to tri-state (deactivate the internal low-side switch) MISO after falling SCK edge. t_RC is the time added by the application total capacitance and resistance.			320+t_RC	ns
t_{ZO_HL}	MISO Drive Time High-to-Low	SSN Falling Edge to MISO Falling			320	ns
t_SS	SSN High Time	How long SSN must remain high between transactions	1000			ns
THERMAL SHUTDOWN
TSD	Thermal shutdown temperature			175		°C
TSD HYST	Thermal shutdown hysteresis			10		°C