6.4 Thermal Information
| THERMAL METRIC(1)(2)
|
TPS7A80 |
UNIT |
| DRB (VSON)(3)
|
| 8 PINS |
| RθJA
|
Junction-to-ambient thermal resistance |
47.8 |
°C/W |
| RθJC(top)
|
Junction-to-case (top) thermal resistance |
53.9 |
°C/W |
| RθJB
|
Junction-to-board thermal resistance |
23.4 |
°C/W |
| ψJT
|
Junction-to-top characterization parameter |
1 |
°C/W |
| ψJB
|
Junction-to-board characterization parameter |
23.5 |
°C/W |
| RθJC(bot)
|
Junction-to-case (bottom) thermal resistance |
7.4 |
°C/W |
(3) Thermal data for the DRB package are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
- The exposed pad is connected to the PCB ground layer through a 2 × 2 thermal via array.
- The top and bottom copper layers are assumed to have a 5% thermal conductivity of copper representing a 20% copper coverage.
- This data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3 inches × 3 inches copper area. To understand the effects of the copper area on thermal performance, refer to the Power Dissipation and Estimating Junction Temperature sections.