ZHCSKH2 November 2019 TPS7A52
ADVANCE INFORMATION for pre-production products; subject to change without notice.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VFB | Feedback voltage | 0.8 | V | |||
| VNR/SS | NR/SS pin voltage | 0.8 | V | |||
| VUVLO+(IN) | Rising input supply UVLO with BIAS | VIN rising with VBIAS = 3 V | 1.02 | 1.085 | V | |
| VUVLO-(IN) | Falling input supply UVLO with BIAS | VIN falling with VBIAS = 3 V | 0.55 | 0.7 | V | |
| VUVLO+(IN) | Rising input supply UVLO without BIAS | VIN rising | 1.31 | 1.39 | V | |
| VUVLO-(IN) | Falling input supply UVLO without BIAS | VIN falling | 0.65 | 1.057 | V | |
| VUVLO+(BIAS) | Rising bias supply UVLO | VBIAS rising, VIN = 1.1 V | 2.83 | 2.9 | V | |
| VUVLO-(BIAS) | Falling bias supply UVLO | VBIAS falling, VIN = 1.1 V | 2.45 | 2.54 | V | |
| VOUT | Output voltage range | 0.8 | 5.2 | V | ||
| VOUT | Output voltage accuracy | 1.4 V ≤ VIN ≤ 6.5 V,
0.8 V ≤ VOUT ≤ 5.2 V, 5 mA ≤ IOUT ≤ 2 A |
–0.75 | 0.75 | % | |
| VIN =1.1 V,
5 mA ≤ IOUT ≤ 2 A, 3 V ≤ VBIAS ≤ 6.5 V |
–0.5 | 0.5 | ||||
| DVOUT/ΔVIN | Line regulation | IOUT = 5 mA,
1.4 V ≤ VIN ≤ 6.5 V |
0.03 | mV/V | ||
| DVOUT/ΔVIN | Load regulation | 5 mA ≤ IOUT ≤ 2 A,
3 V ≤ VBIAS ≤ 6.5 V, VIN = 1.1 V |
0.07 | mV/A | ||
| 5 mA ≤ IOUT ≤ 2 A | 0.012 | |||||
| VOS | Error amplifier offset voltage | VIN = 1.4 V;
IOUT = 5mA; -40℃ ≤ TJ ≤ +125℃ |
–2.5 | 2.5 | mV | |
| VDO | Dropout voltage | VIN = 1.4 V,
IOUT = 2 A, VFB = 0.8 V – 3% |
125 | mV | ||
| VIN = 5.3 V, IOUT = 2 A,
VFB = 0.8 V – 3% |
170 | |||||
| VIN = 5.5 V, IOUT = 2 A,
VFB = 0.8 V – 3% |
225 | |||||
| VIN = 1.1 V,
3.0 V ≤ VBIAS ≤ 6.5 V, IOUT = 2 A, VFB = 0.8 V – 3% |
65 | |||||
| ILIM | Output current limit | VOUT forced at 0.9 × VOUT(nom),
VIN = VOUT(nom) + 0.4 V |
2.7 | 3.3 | 4.0 | A |
| ISC | Short-circuit current limit | RLOAD = 20 mΩ | 2 | A | ||
| IGND | GND pin current | VIN = 6.5 V, IOUT = 5 mA | 2.8 | 4 | mA | |
| VIN = 1.4 V, IOUT = 2 A | 4.8 | 5 | ||||
| Shutdown, PG = open,
VIN = 6.5 V, VEN = 0.5 V |
25 | µA | ||||
| IEN | EN pin current | VIN = 6.5 V,
VEN = 0 V and 6.5 V |
– | 0.5 | µA | |
| IBIAS | BIAS pin current | VIN = 1.1 V, VBIAS = 6.5 V,
VOUT(nom) = 0.8 V, IOUT = 2A |
2.3 | 3.5 | mA | |
| VIL(EN) | EN pin low-level input voltage (disable device) | 0 | 0.5 | V | ||
| VIH(EN) | EN pin high-level input voltage (enable device) | 1.1 | 6.5 | V | ||
| VIT-(PG) | Falling PG pin threshold | For falling VOUT | 82% × VOUT | 88.3% × VOUT | 93% × VOUT | V |
| VIT+(PG) | Rising PG pin threshold | For rising VOUT | 84% × VOUT | 89.3% × VOUT | 95% × VOUT | V |
| VOL(PG) | PG pin low-level output voltage | VOUT < VIT(PG),
IPG = –1 mA (current into device) |
0.4 | V | ||
| Ilkg(PG) | PG pin leakage current | VOUT > VIT(PG), VPG = 6.5 V | 1 | µA | ||
| INR/SS | NR/SS pin charging current | VNR/SS = GND, VIN = 6.5 V | 4 | 6.2 | 9 | |
| IFB | FB pin leakage current | VIN = 6.5 V | – | 100 | nA | |
| RNR | NR resistor value | 250 | kΩ | |||
| PSRR | Power-supply rejection ratio | VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF, f = 10 kHz |
dB | |||
| VIN – VOUT = 0.5 V, VOUT = 0.8 V,
VBIAS = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF, f = 500 kHz |
||||||
| Vn | Output noise voltage | Bandwidth = 10 Hz to 100 kHz,
VIN = 1.1 V, VOUT = 0.8 V, VBIAS = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF |
4.4 | µVRMS | ||
| Bandwidth = 10 Hz to 100 kHz,
VOUT = 5 V, IOUT = 2 A, CNR/SS = 100 nF, CFF = 10 nF, COUT = 47 µF || 10 µF || 10 µF |
8.4 | |||||
| Tsd+ | Thermal shutdown temperature increasing | Shutdown, temperature increasing | 160 | °C | ||
| Tsd- | Thermal shutdown temperature decreasing | Reset, temperature decreasing | 140 | |||