SLVSAE3A August 2010 – January 2016 TPS650231
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Description (continued)
- 6 Pin Configuration and Functions
-
7 Specifications
- 7.1 Absolute Maximum Ratings
- 7.2 ESD Ratings
- 7.3 Recommended Operating Conditions
- 7.4 Thermal Information
- 7.5 Electrical Characteristics
- 7.6 Electrical Characteristics: Control Signals
- 7.7 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3, VINDCDC13
- 7.8 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
- 7.9 Electrical Characteristics: VDCDC1 Step-Down Converter
- 7.10 Electrical Characteristics: VDCDC2 Step-Down Converter
- 7.11 Electrical Characteristics: VDCDC3 Step-Down Converter
- 7.12 Timing Requirements
- 7.13 Typical Characteristics
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagrams
- 8.3
Feature Description
- 8.3.1 VRTC Output and Operation With or Without Backup Battery
- 8.3.2 Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3
- 8.3.3 Power Save Mode Operation
- 8.3.4 Low-Ripple Mode
- 8.3.5 Soft-Start
- 8.3.6 100% Duty Cycle Low-Dropout Operation
- 8.3.7 Active Discharge When Disabled
- 8.3.8 Power-Good Monitoring
- 8.3.9 Low-Dropout Voltage Regulators
- 8.3.10 Undervoltage Lockout
- 8.3.11 Power-Up Sequencing
- 8.3.12 System Reset + Control Signals
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 VERSION Register Address: 00h (Read Only)
- 8.6.2 PGOODZ Register Address: 01h (Read Only)
- 8.6.3 MASK Register Address: 02h (Read or Write), Default Value: C0h
- 8.6.4 REG_CTRL Register Address: 03h (Read or Write), Default Value: FFh
- 8.6.5 CON_CTRL Register Address: 04h (Read or Write), Default Value: B1h
- 8.6.6 CON_CTRL2 Register Address: 05h (Read or Write), Default Value: 40h
- 8.6.7 DEFCORE Register Address: 06h (Read or Write), Default Value: 14h/1Eh
- 8.6.8 DEFSLEW Register Address: 07h (Read or Write), Default Value: 06h
- 8.6.9 LDO_CTRL Register Address: 08h (Read or Write), Default Value: Set with DEFLDO1 and DEFLDO2
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- RSB|40
訂購信息
7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VI | Input voltage range on all pins except AGND and PGND pins with respect to AGND | –0.3 | 7 | V |
| Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 | 2500 | mA | ||
| Peak current at all other pins | 1000 | mA | ||
| TA | Operating free-air temperature | –40 | 85 | °C |
| TJ | Junction temperature | 125 | °C | |
| Tstg | Storage temperature | –65 | 150 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC | Input voltage range step-down converters (VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail |
2.5 | 6 | V | |
| VO | Output voltage range for VDCDC1 step-down converter(1) | 0.6 | VINDCDC1 | V | |
| Output voltage range for VDCDC2 step-down converter(1) | 0.6 | VINDCDC2 | |||
| Output voltage range for VDCDC3 step-down converter(1) | 0.6 | VINDCDC3 | |||
| VI | Input voltage range for LDOs (VINLDO) | 1.5 | 6.5 | V | |
| VO | Output voltage range for LDOs (VLDO1, VLDO2) | 1 | VINLDO1-2 | V | |
| IO(DCDC1) | Output current at L1 | 1700 | mA | ||
| Inductor at L1(2) | 1.5 | 2.2 | μH | ||
| CI(DCDC1) | Input capacitor at VINDCDC1(2) | 10 | μF | ||
| CO(DCDC1) | Output capacitor at VDCDC1(2) | 10 | 22 | μF | |
| IO(DCDC2) | Output current at L2 | 1200 | mA | ||
| Inductor at L2(2) | 1.5 | 2.2 | μH | ||
| CI(DCDC2) | Input capacitor at VINDCDC2(2) | 10 | μF | ||
| CO(DCDC2) | Output capacitor at VDCDC2(2) | 10 | 22 | μF | |
| IO(DCDC3) | Output current at L3 | 800 | mA | ||
| Inductor at L3(2) | 1.5 | 2.2 | μH | ||
| CI(DCDC3) | Input capacitor at VINDCDC3(2) | 10 | μF | ||
| CO(DCDC3) | Output capacitor at VDCDC3(2) | 10 | 22 | μF | |
| CI(VCC) | Input capacitor at VCC(2) | 1 | μF | ||
| CI(VINLDO) | Input capacitor at VINLDO(2) | 1 | μF | ||
| CO(VLDO1-2) | Output capacitor at VLDO1, VLDO2(2) | 2.2 | μF | ||
| IO(VLDO1-2) | Output current at VLDO1, VLDO2 | 200 | mA | ||
| CO(VRTC) | Output capacitor at VRTC(2) | 4.7 | μF | ||
| TA | Operating ambient temperature | –40 | 85 | °C | |
| TJ | Operating junction temperature | –40 | 125 | °C | |
| Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(3) | 1 | 10 | Ω | ||
(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
(2) See Application Information section for more information
(3) Up to 3 mA can flow into VCC when all 3 converters are running in PWM. This resistor causes the UVLO threshold to be shifted accordingly.
7.4 Thermal Information
| THERMAL METRIC(1) | TPS650231 | UNIT | ||
|---|---|---|---|---|
| RSB (VQFN) | YFF (DSBGA) | |||
| 40 PINS | 49 BALLS | |||
| RθJA | Junction-to-ambient thermal resistance | 32.7 | 40 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 15.3 | 10 | °C/W |
| RθJB | Junction-to-board thermal resistance | 13.6 | 15 | °C/W |
| ψJT | Junction-to-top characterization parameter | 0.1 | 0.1 | °C/W |
| ψJB | Junction-to-board characterization parameter | 5.4 | 14 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 1.1 | N/A | °C/W |
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
7.5 Electrical Characteristics
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VLDO1 AND VLDO2 LOW-DROPOUT REGULATORS | ||||||
| VI | Input voltage range for LDO1, 2 | 1.5 | 6.5 | V | ||
| VO(LD01) | LDO1 output voltage range | 1 | 3.15 | V | ||
| VO(LDO2) | LDO2 output voltage range | 1.05 | 3.3 | V | ||
| IO | Maximum output current for LDO1, LDO2 | VI = 1.8 V, VO = 1.3 V | 200 | mA | ||
| VI = 1.5 V, VO = 1.3 V | 120 | |||||
| I(SC) | LDO1 and LDO2 short-circuit current limit | V(LDO1) = GND, V(LDO2) = GND | 400 | mA | ||
| Minimum voltage drop at LDO1, LDO2 | IO = 50 mA, VINLDO = 1.8 V | 120 | mV | |||
| IO = 50 mA, VINLDO = 1.5 V | 65 | 150 | ||||
| IO = 200 mA, VINLDO = 1.8 V | 300 | |||||
| Output voltage accuracy for LDO1, LDO2 | IO = 10 mA | –2% | 1% | |||
| Line regulation for LDO1, LDO2 | VINLDO1, 2 = VLDO1,2 + 0.5 V (min. 2.5 V) to 6.5 V, IO = 10 mA |
–1% | 1% | |||
| Load regulation for LDO1, LDO2 | IO = 0 mA to 50 mA | –1% | 1% | |||
| Regulation time for LDO1, LDO2 | Load change from 10% to 90% | 10 | μs | |||
| ANALOGIC SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3 | ||||||
| VIH | High-level input voltage | 1.3 | VCC | V | ||
| VIL | Low-level input voltage | 0 | 0.1 | V | ||
| Input bias current | 0.001 | 0.05 | μA | |||
| THERMAL SHUTDOWN | ||||||
| T(SD) | Thermal shutdown | Increasing junction temperature | 160 | °C | ||
| Thermal shutdown hysteresis | Decreasing junction temperature | 20 | °C | |||
| INTERNAL UNDERVOLTAGE LOCKOUT | ||||||
| UVLO | Internal UVLO | VCC falling | –2% | 2.35 | 2% | V |
| V(UVLO_HYST) | Internal UVLO comparator hysteresis | 120 | mV | |||
| VOLTAGE DETECTOR COMPARATOR INPUTS PWRFAIL_SNS, LOWBAT_SNS | ||||||
| Comparator threshold (PWRFAIL_SNS, LOWBAT_SNS) LOWBAT_SNS for TPS650231RSB only |
Falling threshold | –1% | 1 | 1% | V | |
| Hysteresis | 40 | 50 | 60 | mV | ||
| Propagation delay | 25-mV overdrive | 10 | μs | |||
| ILK | Input leakage current | 0.001 | 0.1 | μA | ||
| POWER-GOOD | ||||||
| V(PGOODF) | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, decreasing | –12% | –10% | –8% | ||
| V(PGOODR) | VDCDC1, VDCDC2, VDCDC3, VLDO1, VLDO2, increasing | –7% | –5% | –3% | ||
(1) Typical values are at TA = 25°C
7.6 Electrical Characteristics: Control Signals
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SCLK, SDAT (INPUT) | ||||||
| VIH | High level input voltage for the SCLK pin | Rpullup at SCLK = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 5.25 V | 1.4 | VCC | V | |
| VIH | High level input voltage for the SDAT pin | Rpullup at SDAT = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 5.25 V | 1.69 | VCC | V | |
| VIH | High level input voltage for the SDAT pin | Rpullup at SDAT = 4.7 kΩ, pulled to VRTC; For VCC = 2.5 V to 4.5 V | 1.55 | VCC | V | |
| VIL | Low level input voltage | Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC | 0 | 0.35 | V | |
| IH | Input bias current | 0.01 | 0.1 | μA | ||
| HOT_RESET , DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 | ||||||
| VIH | High-level input voltage | 1.3 | VCC | V | ||
| VIL | Low-level input voltage | 0 | 0.4 | V | ||
| IIB | Input bias current | 0.01 | 0.1 | μA | ||
| tdeglitch | Deglitch time at HOT_RESET | 25 | 30 | 35 | ms | |
| LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (OUTPUT) | ||||||
| VOH | High-level output voltage | 6 | V | |||
| VOL | Low-level output voltage | IIL = 5 mA | 0 | 0.3 | V | |
| Duration of low pulse at RESPWRON | External capacitor 1 nF | 100 | ms | |||
| ICONST | Internal charge or discharge current on pin TRESPWRON | Used for generating RESPWRON delay | 1.7 | 2 | 2.3 | μA |
| TRESPWRON_LOWTH | Internal lower comparator threshold on pin TRESPWRON | Used for generating RESPWRON delay | 0.225 | 0.25 | 0.275 | V |
| TRESPWRON_UPTH | Internal upper comparator threshold on pin TRESPWRON | Used for generating RESPWRON delay | 0.97 | 1 | 1.103 | V |
| Resetpwron threshold | VRTC falling | –3% | 2.4 | 3% | V | |
| Resetpwron threshold | VRTC rising | –3% | 2.52 | 3% | V | |
| ILK | Leakage current | Output inactive high | 0.001 | 0.1 | μA | |
(1) Typical values are at TA = 25°C
7.7 Electrical Characteristics: Supply Pins VCC, VINDCDC1, VINDCDC2, VINDCDC3, VINDCDC13
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| I(q) | Operating quiescent current, PFM | All 3 DCDC converters enabled, zero load, and no switching, LDOs enabled; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 85 | 100 | μA | ||
| All 3 DCDC converters enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 78 | 90 | |||||
| DCDC1 and DCDC2 converters enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V |
57 | 70 | |||||
| DCDC1 converter enabled, zero load, and no switching, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 43 | 55 | |||||
| II | Current into VCC; PWM | All 3 DCDC converters enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 2 | 3 | mA | ||
| DCDC1 and DCDC2 converters enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 1.5 | 2.5 | |||||
| DCDC1 converter enabled and running in PWM, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V | 0.85 | 2 | |||||
| I(q) | Quiescent current | All converters disabled, LDOs off; VCC = 3.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V |
23 | 33 | μA | ||
| All converters disabled, LDOs off; VCC = 2.6 V, VBACKUP = 3 V; V(VSYSIN) = 0 V |
3.5 | 5 | μA | ||||
| All converters disabled, LDOs off; VCC = 3.6 V, VBACKUP = 0 V; V(VSYSIN) = 0 V |
43 | μA | |||||
| I(SD) | Shutdown supply current into VINDCDC1 for TPS650231RSB | DCDC1_EN = GND | 0.1 | 1 | μA | ||
| Shutdown supply current into VINDCDC2 for TPS650231RSB | DCDC2_EN = GND | 0.1 | 1 | μA | |||
| Shutdown supply current into VINDCDC3 for TPS650231RSB | DCDC3_EN = GND | 0.1 | 1 | μA | |||
| Shutdown supply current into VINDCDC13 for TPS650231YFF | DCDC1_EN = DCDC3_EN = GND | 0.2 | 2 | μA | |||
(1) Typical values are at TA = 25°C
7.8 Electrical Characteristics: Supply Pins VBACKUP, VSYSIN, VRTC, VINLDO
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | |
|---|---|---|---|---|---|---|
| VBACKUP, VSYSIN, VRTC | ||||||
| I(q) | Operating quiescent current | VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.6 V, current into VBACKUP |
20 | 33 | μA | |
| I(SD) | Operating quiescent current | VBACKUP < V_VBACKUP, current into VBACKUP | 2 | 3 | μA | |
| VRTC LDO output voltage | VSYSIN = VBACKUP = 0 V, IO = 0 mA | 3 | V | |||
| IO | Output current for VRTC | VSYSIN < 2.57 V and VBACKUP < 2.57 V | 30 | mA | ||
| VRTC short-circuit current limit | VRTC = GND; VSYSIN = VBACKUP = 0 V | 100 | mA | |||
| Maximum output current at VRTC for RESPWRON = 1 |
VRTC > 2.6 V, VCC = 3 V;
VSYSIN = VBACKUP = 0 V |
30 | mA | |||
| VO | Output voltage accuracy for VRTC | VSYSIN = VBACKUP = 0 V; IO = 0 mA | –1% | 1% | ||
| Line regulation for VRTC | VCC = VRTC + 0.5 V to 6.5 V, IO = 5 mA | –1% | 1% | |||
| Load regulation VRTC | IO = 1 mA to 30 mA; VSYSIN = VBACKUP = 0 V | –3% | 1% | |||
| Regulation time for VRTC | Load change from 10% to 90% | 10 | μs | |||
| Ilkg | Input leakage current at VSYSIN | VSYSIN < V_VSYSIN | 2 | μA | ||
| rDS(on) of VSYSIN switch | 12.5 | Ω | ||||
| rDS(on) of VBACKUP switch | 12.5 | Ω | ||||
| Input voltage range at VBACKUP | 2.73 | 3.75 | V | |||
| Input voltage range at VSYSIN | 2.73 | 3.75 | V | |||
| VSYSIN threshold | VSYSIN falling | –3% | 2.55 | 3% | V | |
| VSYSIN threshold | VSYSIN rising | –3% | 2.65 | 3% | V | |
| VBACKUP threshold | VBACKUP falling | –3% | 2.55 | 3% | V | |
| VBACKUP threshold | VBACKUP falling | –3% | 2.65 | 3% | V | |
| VINLDO | ||||||
| I(q) | Operating quiescent current | Current per LDO into VINLDO | 20 | 33 | μA | |
| I(SD) | Shutdown current | Total current for both LDOs into VINLDO, VLDO = 0 V |
0.1 | 1 | μA | |
(1) Typical values are at TA = 25°C
7.9 Electrical Characteristics: VDCDC1 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VI | Input voltage range, VINDCDC1 | 2.5 | 6 | V | |||
| IO | Maximum output current | 1700 | mA | ||||
| rDS(on) | P-channel MOSFET ON-resistance | VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V | 125 | 261 | mΩ | ||
| Ilkg | P-channel leakage current | VINDCDC1 (VINDCDC13) = 6 V | 2 | μA | |||
| rDS(on) | N-channel MOSFET ON-resistance | VINDCDC1 (VINDCDC13) = V(GS) = 3.6 V | 130 | 260 | mΩ | ||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | ||
| Forward current limit (P-channel and N-channel) |
2.5 V < V(VINDCDC1) < 6 V | 1.94 | 2.19 | 2.44 | A | ||
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | ||
| Fixed output voltage FPWMDCDC1 = 0; all VDCDC1 |
VINDCDC1 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1.7 A |
–2% | 2% | ||||
| Fixed output voltage FPWMDCDC1 = 1; all VDCDC1 |
VINDCDC1 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 1.7 A |
–1% | 1% | ||||
| Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 0 | VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A |
–2% | 2% | ||||
| Adjustable output voltage with resistor divider at DEFDCDC1; FPWMDCDC1 = 1 | VINDCDC1 (VINDCDC13) = VDCDC1 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.7 A |
–1% | 1% | ||||
| Line regulation | VINDCDC1 (VINDCDC13) = VDCDC1 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA |
0% | V | ||||
| Load regulation | IO = 10 mA to 1700 mA | 0.25% | A | ||||
| tStart | Start-up time | Time from active EN to start switching | 145 | 175 | 200 | μs | |
| tRamp | VOUT ramp-up time | Time to ramp from 5% to 95% of VOUT | 400 | 750 | 1000 | μs | |
| Internal resistance from L1 to GND | 1 | MΩ | |||||
| VDCDC1 discharge resistance | DCDC1 discharge = 1 | 300 | Ω | ||||
(1) Typical values are at TA = 25°C
7.10 Electrical Characteristics: VDCDC2 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VI | Input voltage range, VINDCDC2 | 2.5 | 6 | V | |||
| IO | Maximum output current | VDCDC2 = 1.2V | 1200 | mA | |||
| VINDCDC2 = 3.7 V; 3.3 V – 1% ≤ VDCDC2 ≤ 3.3 V + 1% |
1000 | ||||||
| rDS(on) | P-channel MOSFET ON-resistance | VINDCDC2 = V(GS) = 3.6 V | 140 | 300 | mΩ | ||
| Ilkg | P-channel leakage current | VINDCDC2 = 6 V | 2 | μA | |||
| rDS(on) | N-channel MOSFET ON-resistance | VINDCDC2 = V(GS) = 3.6 V | 150 | 297 | mΩ | ||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | ||
| ILIMF | Forward current limit (P-channel and N-channel) |
2.5 V < VINDCDC2 < 6 V | 1.74 | 1.94 | 2.12 | A | |
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | ||
| VDCDC2 | Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 0 | VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A | –2% | 2% | |||
| VDCDC2 | Adjustable output voltage with resistor divider at DEFDCDC2; FPWMDCDC2 = 1 | VINDCDC2 = VDCDC2 + 0.4 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 1.2 A | –1% | 1% | |||
| Line regulation | VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V) to 6 V; IO = 10 mA | 0% | V | ||||
| Load regulation | IO = 10 mA to 1.2 A | 0.25% | A | ||||
| tStart | Start-up time | Time from active EN to start switching | 145 | 175 | 200 | µs | |
| tRamp | VOUT ramp-up time | Time to ramp from 5% to 95% of VOUT | 400 | 750 | 1000 | μs | |
| Internal resistance from L2 to GND | 1 | MΩ | |||||
| VDCDC2 discharge resistance | DCDC2 discharge = 1 | 300 | Ω | ||||
(1) Typical values are at TA = 25°C
7.11 Electrical Characteristics: VDCDC3 Step-Down Converter
VINDCDC1 = VINDCDC2 = VINDCDC3 (VINDCDC13) = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to +85°C (unless otherwise noted)| PARAMETER | TEST CONDITIONS | MIN | TYP(1) | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| VI | Input voltage range, VINDCDC3 | 2.5 | 6 | V | |||
| IO | Maximum output current | DEFDCDC3 = GND | 800 | mA | |||
| VINDCDC3 (VINDCDC13) = 3.6 V; 3.3 V – 1% ≤ VDCDC3 ≤ 3.3 V + 1% |
525 | ||||||
| rDS(on) | P-channel MOSFET ON-resistance | VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V | 310 | 698 | mΩ | ||
| Ilkg | P-channel leakage current | VINDCDC3 (VINDCDC13) = 6 V | 0.1 | 2 | μA | ||
| rDS(on) | N-channel MOSFET ON-resistance | VINDCDC3 (VINDCDC13) = V(GS) = 3.6 V | 220 | 503 | mΩ | ||
| Ilkg | N-channel leakage current | V(DS) = 6 V | 7 | 10 | μA | ||
| Forward current limit (P-channel and N-channel) |
2.5 V < VINDCDC3 (VINDCDC13) < 6 V | 1.28 | 1.49 | 1.69 | A | ||
| fS | Oscillator frequency | 1.95 | 2.25 | 2.55 | MHz | ||
| Fixed output voltage FPWMDCDC3 = 0 | VDCDC3 = 1.8 V; VINDCDC3 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 0.8 A |
–2% | 2% | ||||
| VDCDC3 = 3.3 V; VINDCDC3 (VINDCDC13) = 3.6 V to 6 V; 0 mA ≤ IO ≤ 0.8 A |
–1% | 1% | |||||
| Fixed output voltage FPWMDCDC3 = 1 | VDCDC3 = 1.8 V; VINDCDC3 (VINDCDC13) = 2.5 V to 6 V; 0 mA ≤ IO ≤ 0.8 A |
–2% | 2% | ||||
| VDCDC3 = 3.3 V; VINDCDC3 (VINDCDC13) = 3.6 V to 6 V; 0 mA ≤ IO ≤ 0.8 A |
–1% | 1% | |||||
| Adjustable output voltage with resistor divider at DEFDCDC3 FPWMDCDC3 = 0 | VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA |
–2% | 2% | ||||
| Adjustable output voltage with resistor divider at DEFDCDC3; FPWMDCDC3 = 1 | VINDCDC3 (VINDCDC13) = VDCDC3 + 0.5 V (min 2.5 V) to 6 V; 0 mA ≤ IO ≤ 800 mA |
–1% | 1% | ||||
| Line regulation | VINDCDC3 (VINDCDC13) = VDCDC3 + 0.3 V (min 2.5 V) to 6 V; IO = 10 mA |
0% | V | ||||
| Load regulation | IO = 10 mA to 800 mA | 0.25% | A | ||||
| tStart | Start-up time | Time from active EN to start switching | 145 | 175 | 200 | µs | |
| tRamp | VOUT ramp-up time | Time to ramp from 5% to 95% of VOUT | 400 | 750 | 1000 | μs | |
| Internal resistance from L3 to GND | 1 | MΩ | |||||
| VDCDC3 discharge resistance | DCDC3 discharge = 1 | 300 | Ω | ||||
(1) Typical values are at TA = 25°C
7.12 Timing Requirements
Operating conditions: VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5 V to 5.5 V, VBACKUP = 3.0 V,TA = –40°C to +85°C
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| fMAX | Clock frequency | 400 | kHz | ||
| twH(HIGH) | Clock high time | 600 | ns | ||
| twL(LOW) | Clock low time | 1300 | ns | ||
| tR | DATA and CLK rise time | 300 | ns | ||
| tF | DATA and CLK fall time | 300 | ns | ||
| th(STA) | Hold time (repeated) START condition (after this period the first clock pulse is generated) | 600 | ns | ||
| tsu(DATA) | Setup time for repeated START condition | 600 | ns | ||
| th(DATA) | Data input hold time | 100 | ns | ||
| tsu(DATA) | Data input setup time | 100 | ns | ||
| tsu(STO) | STOP condition setup time | 600 | ns | ||
| t(BUF) | Bus free time | 1300 | ns | ||
Figure 1. Serial I/F Timing Diagram
Figure 2. HOT_RESET Timing (TPS650231RSB Only)
Figure 3. Power-Up and Power-Down Timing
Figure 4. DVS Timing
7.13 Typical Characteristics
Table 1. Table of Graphs
| FIGURE | |||
|---|---|---|---|
| η | Efficiency | vs Output current | Figure 5, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 |
| Output voltage | vs Output current at 85°C | Figure 11, Figure 12 | |
| Line transient response | Figure 13, Figure 14, Figure 15 | ||
| Load transient response | Figure 16, Figure 17, Figure 18 | ||
| VDCDC2 PFM operation | Figure 19 | ||
| VDCDC2 low-ripple PFM operation | Figure 20 | ||
| VDCDC2 PWM operation | Figure 21 | ||
| Start-up VDCDC1, VDCDC2 and VDCDC3 | Figure 22 | ||
| Start-up LDO1 and LDO2 | Figure 23 | ||
| Line transient response | Figure 24, Figure 25, Figure 26 | ||
| Load transient response | Figure 27, Figure 28, Figure 29 | ||
Figure 5. DCDC1: Efficiency vs Output Current
Figure 7. DCDC2: Efficiency vs Output Current
Figure 9. DCDC3: Efficiency vs Output Current
Figure 11. DCDC2: Output Voltage vs Output Current at 85°C
Figure 13. VDCDC1 Line Transient Response
Figure 15. VDCDC3 Line Transient Response
Figure 17. VDCDC2 Load Transient Response
Figure 19. VDCDC2 Output Voltage Ripple
Figure 21. VDCDC2 Output Voltage Ripple
Figure 23. Start-Up LDO1 and LDO2
Figure 25. LDO2 Line Transient Response
Figure 27. LDO1 Load Transient Response
Figure 29. VRTC Load Transient Response
Figure 6. DCDC1: Efficiency vs Output Current
Figure 8. DCDC2: Efficiency vs Output Current
Figure 10. DCDC3: Efficiency vs Output Current
Figure 12. DCDC3: Output Voltage vs Output Current at 85°C
Figure 14. VDCDC2 Line Transient Response
Figure 16. VDCDC1 Load Transient Response
Figure 18. VDCDC3 Load Transient Response
Figure 20. VDCDC2 Output Voltage Ripple
Figure 22. Start-Up VDCDC1, VDCDC2, and VDCDC3
Figure 24. LDO1 Line Transient Response
Figure 26. VRTC Line Transient Response
Figure 28. LDO2 Load Transient Response