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ZHCSBR7C August 2013 – June 2017 TPS65000-Q1

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

RTE|16
- MPQF149D

散熱焊盤機械數據 (封裝 | 引腳)

RTE|16
- QFND525B

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	On all pins except AGND, PGND, EN_DCDC, VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC pins with respect to AGND	–0.3	7	V
Input voltage	On EN_DCDC with respect to AGND	–0.3	V_IN + 0.3, ≤ 7	V
Output voltage	On VLDO1, VLDO2, FB_LDO1, FB_LDO2, FB_DCDC	–0.3	3.6	V
Current	VINDCDC, SW, PGND,		1800	mA
	VINLDO1, VINLDO2, VLDO1, VLDO1, AGND		800	mA
	At all other pins		1	mA
Operating free-air temperature, T_A		–40	105	°C
Maximum junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002⁽¹⁾		±2500	V
		Charged device model (CDM), per AEC Q100-011	Corner pins (1, 4, 5, 8, 9, 12, 13, and 16)	±750
		Charged device model (CDM), per AEC Q100-011	Other pins	±500

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

		MIN	NOM	MAX	UNIT
L1	SW pin inductor	1.5	2.2	3.3	μH
C_I	Input capacitor at VINDCDC	10			μF
C_I	Input capacitor at VINLDO1, VINLDO2	2.2			μF
C_O	Output capacitor for VDCDC	10		22	μF
C_O	Output capacitor for LDO1, LDO2	2.2			μF
I_O	DC-DC converter output current			600	mA
	LDO1 output current			300	mA
	LDO2 output current			300	mA
T_A	Operating ambient temperature	–40		105	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS65000-Q1	UNIT
		RTE (WQFN)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance	46.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	56.1	°C/W
R_θJB	Junction-to-board thermal resistance	19.2	°C/W
ψ_JT	Junction-to-top characterization parameter	1.1	°C/W
ψ_JB	Junction-to-board characterization parameter	19.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	5.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Over full operating ambient temperature range, typical values are at T_A = 25° C. Unless otherwise noted, specifications apply for condition V_IN = EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 μH, C_OUT = 10 μF, C_IN = 4.7 μF.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
OPERATING VOLTAGE
V_IN	Input voltage for VINDCDC of DC-DC converter		2.3		6	V
	Input voltage for LDO1 (VINLDO1)	See ⁽¹⁾	1.6		6	V
	Input voltage for LDO2 (VINLDO2)	See ⁽¹⁾	1.6		6	V
	Internal undervoltage (UVLO) lockout threshold	V_CC falling	1.72	1.77	1.82	V
	Internal undervoltage (UVLO) lockout hysteresis			160		mV
SUPPLY CURRENT
I_Q	Operating quiescent current	MODE low, EN_DCDC high, EN_LDO1, EN_LDO2 low, I_OUT = 0 mA and no switching		23	32	μA
		MODE low, EN_DCDC low, EN_LDO1, EN_LDO2 high, I_OUT = 0 mA I_OUT = 0 mA and no switching		50	57	μA
		EN_DCDC high, MODE high, EN_LDO1, EN_LDO2 low, I_OUT = 0 mA		4		mA
I_SD	Shutdown Current	EN_DCDC low EN_LDO1 and EN_LDO2 low		0.16	2.2	μA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG
V_IH	High-level input voltage		1.2			V
V_IL	Low-level input voltage				0.4	V
V_OL	Low-level output voltage	PG pins only, I_O = –100 μA			0.4	V
I_lkg	Input leakage current	MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to GND or VINDCDC		0.01	0.1	μA
OSCILLATOR
f_SW	Oscillator frequency	SSCG enabled, SSC modulation ratio = 16%	1.722	2.25	2.847	MHz
f_SW	Oscillator frequency	SSCG disabled, SSC modulation ratio disabled	2.01	2.25	2.41	MHz
STEP-DOWN CONVERTER POWER SWITCH
r_DS(on)	High-side MOSFET ON-resistance	VINDCDC = V_GS = 3.6 V		240	480	mΩ
r_DS(on)	Low-side MOSFET ON-resistance	VINDCDC = V_GS = 3.6 V		185	380	mΩ
I_O	DC output current	2.3 V ≤ VINDCDC ≤ 2.5 V			300	mA
I_O	DC output current	2.5 V ≤ VINDCDC ≤ 6 V			600	mA
I_LIMF	Forward current limit, PMOS and NMOS	2.3 V ≤ VINDCDC ≤ 6 V	800	1000	1400	mA
STEP-DOWN CONVERTER POWER SWITCH (continued)
T_SD	Thermal shutdown	Increasing junction temperature		150		°C
T_SD	Thermal shutdown hysteresis	Decreasing junction temperature		30		°C
STEP-DOWN CONVERTER OUTPUT VOLTAGE
VDCDC	Adjustable output voltage range, VDCDC		0.6		VINDCDC	V
	FB_DCDC pin current				0.1	μA
V_ref	Internal reference voltage		0.594	0.6	0.606	V
VDCDC	Output-voltage accuracy (PWM mode)⁽²⁾	MODE = high, 2.3 ≤ VINDCDC ≤ 6 V	–1.5%	0%	1.5%
VDCDC	Output-voltage accuracy (PFM mode) ⁽³⁾	MODE low +1% voltage positioning active		1%
	Load regulation (PWM mode)	MODE high		0.5		%/A
R_DIS	Internal discharge resistance at SW	EN_DCDC low		450		Ω
LOW-DROPOUT REGULATORS
V_I	Input voltage for LDOx (VINLDOx)		1.6		6	V
V_O	Adjustable output voltage, LDOx (VLDOx)⁽⁴⁾		0.73		VINLDOx – V_DO	V
I_O	Continuous-pass FET current				300	mA
I_SC	Short-circuit current limit	2.3 V ≤ VINLDOx	340		700	mA
I_SC	Short-circuit current limit	VINLDOx < 2.3 V	210		700	mA
	FB_LDOx pin current				0.1	μA
	FB_LDOx voltage	Adjustable V_OUT mode only		0.5		V
V_DO	Dropout voltage ⁽⁵⁾	VINLDOx ≥ 2.3 V, I_OUT = 250 mA			370	mV
V_DO	Dropout voltage ⁽⁵⁾	VINLDOx < 2.3 V, I_OUT = 175 mA			370	mV
	Output voltage accuracy ⁽⁶⁾	I_O = 1 mA to 300 mA, VINLDOx = 2.3 V–6 V, VLDOx = 1.2 V	–3.5%		3.5%
	Output voltage accuracy ⁽⁶⁾	I_O = 1 mA to 175 mA, VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V	–3.5%		3.5%
	Load regulation	I_O = 1 mA to 300 mA, VINLDOx = 3.6 V VLDOx = 1.2 V	–1.5%		1.5%
	Line regulation	VINLDOx = 1.6 V–6 V, VLDOx = 1.2 V at I_O = 1 mA	–0.5%		0.5%
PSRR	Power-supply rejection ratio	f_NOISE ≤ 10 kHz, C_OUT ≥ 2.2 μF, V_IN = 2.3 V, V_OUT = 1.3 V, I_OUT = 10 mA		40		dB
R_DIS	Internal discharge resistance at VLDOx	EN_LDOx low		450		Ω
T_SD	Thermal shutdown	Increasing temperature		150		°C
	Thermal shutdown hysteresis	Decreasing temperature		30		°C

(1) The design principle allows only VINDCDC to be the highest supply in the system. If separate input voltage supplies are used for the DC-DC converter and LDOs, then choose VINDCDC ≥ VINLDO1 and VINDCDC ≥ VINLDO2.

(2) For VINDCDC = VDCDC + 1 V

(3) In PFM mode, the internal reference voltage is typically 1.01 × V_REF.

(4) Maximum output voltage VLDOx = 3.6 V.

(5) V_DO = VINLDOx – VLDOx, where VINLDOx = VLDOx(nom) – 100 mV

(6) Output voltage specification does not include tolerance of external programming resistors.

6.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	UNIT
STEP-DOWN CONVERTER OUTPUT VOLTAGE
t_Start	Start-up time	EN_DCDC to start of switching (10%)	250	µs
t_Ramp	VDCDC ramp-up time	VDCDC ramp from 10% to 90%	250	µs
LOW-DROPOUT REGULATORS
t_RAMP	VLDOx ramp time	VLDOx ramp from 10% to 90%	200	µs