ZHCSLS6B August 2020 – June 2022 TPS628510 , TPS628511 , TPS628512 , TPS628513
PRODUCTION DATA
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| IQ | Quiescent current | EN = VIN, no load, device not switching, MODE = GND, VOUT = 0.6 V | 17 | 36 | μA | |
| ISD | Shutdown current | EN = GND, nominal value at TJ = 25°C, maximum value at TJ = 150°C | 1.5 | 48 | μA | |
| VUVLO | Undervoltage lockout threshold | VIN rising | 2.45 | 2.6 | 2.7 | V |
| VIN falling | 2.1 | 2.5 | 2.6 | V | ||
| TJSD | Thermal shutdown threshold | TJ rising | 170 | °C | ||
| Thermal shutdown hysteresis | TJ falling | 15 | °C | |||
| CONTROL AND INTERFACE | ||||||
| VEN,IH | Input threshold voltage at EN, rising edge | 1.05 | 1.1 | 1.15 | V | |
| VEN,IL | Input threshold voltage at EN, falling edge | 0.96 | 1.0 | 1.05 | V | |
| VIH | High-level input-threshold voltage at MODE/SYNC | 1.1 | V | |||
| IEN,LKG | Input leakage current into EN | VIH = VIN or VIL = GND | 125 | nA | ||
| VIL | Low-level input-threshold voltage at MODE/SYNC | 0.3 | V | |||
| ILKG | Input leakage current into MODE/SYNC | 100 | nA | |||
| tDelay | Enable delay time | Time from EN high to device starts switching; VIN applied already | 85 | 150 | 470 | μs |
| tRamp | Output voltage ramp time | Time from device starts switching to power good; device not in current limit | 0.8 | 1.3 | 1.8 | ms |
| tRamp | Output voltage ramp time, SS/TR pin open | Time from device starts switching to power good; device not in current limit | 90 | 150 | 210 | μs |
| ISS/TR | SS/TR source current | 2 | 2.5 | 2.8 | μA | |
| Tracking gain | VFB / VSS/TR | 1 | ||||
| Tracking offset | VFB when VSS/TR = 0 V | ±1 | mV | |||
| fSYNC | Frequency range on MODE/SYNC pin for synchronization | 1.8 | 4 | MHz | ||
| Duty cycle of synchronization signal at MODE/SYNC | 20% | 80% | ||||
| Time to lock to external frequency | 50 | μs | ||||
| VTH_PG | UVP power-good
threshold voltage; DC level |
Rising (%VFB) | 92% | 95% | 98% | |
| VTH_PG | UVP power-good
threshold voltage; DC level |
Falling (%VFB) | 87% | 90% | 93% | |
| VTH_PG | OVP power-good
threshold voltage; DC level |
Rising (%VFB) | 107% | 110% | 113% | |
| OVP power-good
threshold voltage; DC level |
Falling (%VFB) | 104% | 107% | 111% | ||
| VPG,OL | Low-level output voltage at PG | ISINK_PG = 2 mA | 0.07 | 0.3 | V | |
| IPG,LKG | Input leakage current into PG | VPG = 5 V | 100 | nA | ||
| tPG | PG deglitch time | For a high level to low level transition on the power-good output | 40 | μs | ||
| OUTPUT | ||||||
| VFB | Feedback voltage, adjustable version | 0.6 | V | |||
| IFB,LKG | Input leakage current into FB, adjustable version | VFB = 0.6 V | 1 | 70 | nA | |
| VFB | Feedback voltage accuracy | PWM, VIN ≥ VOUT + 1 V | –1% | 1% | ||
| VFB | Feedback voltage accuracy | PFM, VIN ≥ VOUT + 1 V, VOUT ≥ 1.0 V, Co,eff ≥ 10 μF, L = 0.47μH | –1% | 2% | ||
| VFB | Feedback voltage accuracy | PFM, VIN ≥ VOUT + 1 V, VOUT < 1.0 V, Co,eff ≥ 15 μF, L = 0.47 μH | –1% | 3% | ||
| VFB | Feedback voltage accuracy with voltage tracking | VIN ≥ VOUT + 1 V, VSS/TR = 0.3 V | –4% | 4% | ||
| Load regulation | PWM | 0.05 | %/A | |||
| Line regulation | PWM, IOUT = 1 A, VIN ≥ VOUT + 1 V | 0.02 | %/V | |||
| RDIS | Output discharge resistance | 100 | Ω | |||
| fSW | PWM switching frequency | 2.025 | 2.25 | 2.475 | MHz | |
| ton,min | Minimum on time of high-side FET | VIN = 3.3 V, TJ = –40°C to 125°C | 35 | 52 | ns | |
| ton,min | Minimum on time of low-side FET | 10 | ns | |||
| RDS(ON) | High-side FET on-resistance | VIN ≥ 5 V | 65 | 120 | mΩ | |
| Low-side FET on-resistance | VIN ≥ 5 V | 33 | 70 | mΩ | ||
| High-side MOSFET leakage current | 0.01 | 44 | μA | |||
| Low-side MOSFET leakage current | 0.01 | 70 | μA | |||
| SW leakage | V(SW) = 0.6 V, current into SW | –0.05 | 11 | μA | ||
| ILIMH | High-side FET switch current limit | DC value, for TPS628513; VIN = 3 V to 6 V |
3.45 | 4.5 | 5.1 | A |
| ILIMH | High-side FET switch current limit | DC value, for TPS628512; VIN = 3 V to 6 V |
2.85 | 3.4 | 3.9 | A |
| ILIMH | High-side FET switch current limit | DC value, for TPS628511; VIN = 3 V to 6 V |
2.1 | 2.6 | 3.0 | A |
| ILIMH | High-side FET switch current limit | DC value, for TPS628510; VIN = 3 V to 6 V |
1.6 | 2.1 | 2.5 | A |
| ILIMNEG | Low-side FET negative current limit | DC value | –1.8 | A | ||