SLVSAO5B December 2010 – October 2015 TPS62590-Q1
PRODUCTION DATA.
| MIN | MAX | UNIT | |||
|---|---|---|---|---|---|
| VI | Input voltage(2) | –0.3 | 7 | V | |
| Voltage range at EN, MODE | –0.3 | VIN +0.3, ≤ 7 | V | ||
| Voltage on SW | –0.3 | 7 | V | ||
| Peak output current | Internally limited | A | |||
| TJ | Maximum operating junction temperature | –40 | 125 | °C | |
| Tstg | Storage temperature | –65 | 150 | °C | |
| VALUE | UNIT | ||||
|---|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per AEC Q100-002(1) | ±2000 | V | |
| Charged-device model (CDM), per AEC Q100-011 | ±1000 | ||||
| THERMAL METRIC(1)(2) | TPS62590-Q1 | UNIT | |
|---|---|---|---|
| DRV (SON) | |||
| 6 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 67.8 | °C/W |
| RθJC(top) | Junction-to-case (top) thermal resistance | 88.5 | °C/W |
| RθJB | Junction-to-board thermal resistance | 37.2 | °C/W |
| ψJT | Junction-to-top characterization parameter | 2 | °C/W |
| ψJB | Junction-to-board characterization parameter | 37.6 | °C/W |
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | 7.9 | °C/W |
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| SUPPLY | ||||||
| VI | Input voltage range | 2.5 | 6 | V | ||
| IO | Output current(4) | VIN 2.7 V to 6 V | 1000 | mA | ||
| VIN 2.5 V to 2.7 V | 600 | |||||
| IQ | Operating quiescent current | IO = 0 mA, PFM mode enabled (MODE = GND) device not switching, See (1) |
15 | μA | ||
| IO = 0 mA, switching with no load (MODE = VIN) PWM mode, VO = 1.8 V, VIN = 3 V |
3.8 | mA | ||||
| ISD | Shutdown current | EN = GND | 0.5 | μA | ||
| UVLO | Undervoltage lockout threshold | Falling | 1.85 | V | ||
| Rising | 1.95 | |||||
| ENABLE, MODE | ||||||
| VIH | High-level input voltage, EN, MODE | 2.5 V ≤ VIN ≤ 6 V | 1 | VIN | V | |
| VIL | Low-level input voltage, EN, MODE | 2.5 V ≤ VIN ≤ 6 V | 0 | 0.4 | V | |
| II | Input bias current, EN, MODE | EN, MODE = GND or VIN | 0.01 | 1 | μA | |
| POWER SWITCH | ||||||
| rDS(on) | High-side MOSFET on-resistance | VIN = VGS = 3.6 V, TA = 25°C | 250 | mΩ | ||
| Low-side MOSFET on-resistance | 190 | |||||
| ILIMF | Forward current limit MOSFET high-side and low-side | VIN = VGS = 3.6 V, TA = 25°C | 1.19 | 1.4 | 1.78 | A |
| TSD | Thermal shutdown | Increasing junction temperature | 140 | °C | ||
| Thermal shutdown hysteresis | Decreasing junction temperature | 20 | ||||
| OSCILLATOR | ||||||
| fSW | Oscillator frequency | 2.5 V ≤ VIN ≤ 6 V | 2.25 | MHz | ||
| OUTPUT | ||||||
| VO | Adjustable output voltage range | 0.75 | VI | V | ||
| Vref | Reference voltage | 600 | mV | |||
| VFB(PWM) | Feedback voltage | MODE = VIN, PWM mode, 2.5 V ≤ VIN ≤ 6 V, See (2) |
–2.5% | 0% | 2.5% | |
| VFB(PFM) | Feedback voltage, PFM mode | MODE = GND, device in PFM mode, 1% voltage positioning active, See (1) | 1% | |||
| Load regulation | –1 | %/A | ||||
| tStart Up | Start-up time | Time from active EN to reach 95% of VO | 500 | μs | ||
| tRamp | VO ramp-up time | Time to ramp from 5% to 95% of VO | 250 | μs | ||
| Ilkg | Leakage current into SW pin | VI = 3.6 V, VI = VO = VSW, EN = GND, See (3) |
0.1 | 1 | μA | |
| FIGURE | ||
|---|---|---|
| Efficiency | vs Output Current VOUT = 1.8 V (Power-Save Mode) | Figure 1 |
| vs Output Current VOUT = 1.8 V (Forced PWM Mode) | Figure 2 | |
| vs Output Current VOUT = 3.3 V (Power-Save Mode) | Figure 3 | |
| vs Output Current VOUT = 3.3 V (Forced PWM Mode) | Figure 4 | |
| Output Voltage | vs Output Current VOUT = 1.8 V (Forced PWM Mode) | Figure 5 |
| vs Output Current VOUT = 1.8 V (Power-Save Mode) | Figure 6 | |
| vs Output Current VOUT = 3.3 V (Forced PWM Mode) | Figure 7 | |
| vs Output Current VOUT = 3.3 V (Power-Save Mode) | Figure 8 | |
| Transient Behavior | PFM to PWM to PFM Load Transient | Figure 9 |
| PWM Load Transient | Figure 10 | |
| PFM Line Transient | Figure 11 | |
| PWM Line Transient | Figure 12 | |
| Typical Performance – PFM Mode | Figure 13 | |
| Typical Performance – PWM Mode | Figure 14 | |
| Shutdown Current | into VIN vs. Input Voltage | Figure 15 |
| Quiescent Current | vs Input Voltage | Figure 16 |
| Static Drain-Source On-State Resistance | vs Input Voltage | Figure 17 |
| Figure 18 | ||