ZHCS984B June 2012 – May 2019 TPS54678
PRODUCTION DATA.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT |
|---|---|---|---|---|---|
| SUPPLY VOLTAGE (VIN PIN) | |||||
| Operating input voltage | 2.95 | 6 | V | ||
| Shutdown supply current | EN = 0 V, 25°C, 2.95 V ≤ VIN ≤ 6 V | 1 | 3 | µA | |
| Operating non-switching supply current | VSENSE = 0.6 V, VIN = 5 V, 25°C, fSW = 500 kHz | 570 | 800 | µA | |
| ENABLE AND UVLO (EN PIN) | |||||
| Enable threshold | Rising | 1.3 | V | ||
| Enable threshold | Falling | 1.18 | V | ||
| Input current | Enable threshold + 50 mV | –3.5 | µA | ||
| Input current | Enable threshold – 50 mV | –0.70 | µA | ||
| VOLTAGE REFERENCE | |||||
| Voltage reference | 2.95 V ≤ VIN ≤ 6 V, –40°C < TJ < 150°C | 0.594 | 0.600 | 0.606 | V |
| MOSFET | |||||
| High-side switch resistance | BOOT-PH = 5 V | 12 | 25 | mΩ | |
| High-side switch resistance | BOOT-PH = 2.95 V | 17 | 33 | ||
| Low-side switch resistance | BOOT-PH = 5 V | 12 | 25 | mΩ | |
| Low-side switch resistance | BOOT-PH = 2.95 V | 17 | 33 | ||
| ERROR AMPLIFIER | |||||
| Input current | 7 | nA | |||
| Error amplifier transconductance (gm) | –2 µA < I(COMP) < 2 µA V(COMP) = 1 V | 245 | umhos | ||
| Error amplifier transconductance (gm) during slow-start | –2 µA < I(COMP) < 2 µA V(COMP) = 1 V, V(VSENSE) = 0.4 V | 80 | umhos | ||
| Error amplifier source and sink | V(COMP) = 1 V 100-mV overdrive | ±20 | µA | ||
| COMP to Iswitch gm | 20 | A/V | |||
| CURRENT LIMIT | |||||
| Current limit threshold | Fs = 500 KHz | 9.5 | 10.5 | 11.5 | A |
| Cycles before entering hiccup during overcurrent | 512 | cycles | |||
| Hiccup cycles | 16384 | cycles | |||
| Low-side sourcing current threshold | 7 | 8.5 | 10.5 | A | |
| Low-side FET reverse current protection | 4 | A | |||
| THERMAL SHUTDOWN | |||||
| Thermal shutdown | 170 | °C | |||
| Hysteresis | 15 | °C | |||
| TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN) | |||||
| Switching frequency range using RT mode | 200 | 2000 | kHz | ||
| Switching frequency | Rt = 82.5 kΩ | 400 | 500 | 600 | kHz |
| Switching frequency range using CLK mode | 300 | 2000 | kHz | ||
| Minimum CLK pulse width | 75 | ns | |||
| RT/CLK voltage | R(RT/CLK) = 82.5 kΩ | 0.5 | V | ||
| RT/CLK high threshold | 1.6 | 2.2 | V | ||
| RT/CLK low threshold | 0.4 | 0.6 | V | ||
| RT/CLK falling edge to PH rising edge delay | Measure at 500 kHz with RT resistor in series | 55 | ns | ||
| PLL lock in time | Measure at 500 kHz | 40 | µs | ||
| PH (PH PIN) | |||||
| Minimum ON-time | Measured at 50% points on PH. IOUT = 3 A | 85 | 110 | ns | |
| Measured at 50% points on PH. IOUT = 0 A | 100 | ns | |||
| Minimum OFF-time | Prior to skipping off pulses,
BOOT-PH = 3 V, IOUT = 3 A |
70 | ns | ||
| Rise and fall dV/dT | BOOT-PH = 3 V; IO = 6 A | 1.5 | V/ns | ||
| BOOT (BOOT PIN) | |||||
| Charging resistor | VIN = 6 V, BOOT-PH = 6 V | 7 | Ω | ||
| BOOT-PH UVLO | VIN = 3.3 V | 2.2 | V | ||
| SLOW START AND TRACKING (SS/TR PIN) | |||||
| Charge current | V(SS/TR) < 0.15 V | 47 | µA | ||
| V(SS/TR) > 0.15 V | 2.2 | ||||
| SS/TR to VSENSE matching | VIN = 3.3 V | 60 | mV | ||
| SS/TR to reference crossover | 98% nominal | 0.8 | V | ||
| SS/TR discharge voltage (overload) | VSENSE = 0 V | 4.5 | mV | ||
| SS/TR discharge to current (overload) | VSENSE = 0 V; V(SS/TR) = 4 V | 95 | µA | ||
| SS/TR discharge current (UVLO, EN, thermal fault) | VIN = 3 V; V(SS/TR) = 4 V | 925 | µA | ||
| POWER GOOD (PWRGD PIN) | |||||
| VSENSE threshold | VSENSE falling (Fault) | 91 | % VREF | ||
| VSENSE rising (Good) | 93 | % VREF | |||
| VSENSE rising (Fault) | 105 | % VREF | |||
| VSENSE falling (Good) | 103 | % VREF | |||
| Output high leakage | VSENSE = VREF, V(PWRGD) = 5.5 V | 2 | nA | ||
| ON-Resistance | VIN = 5 V | 65 | 120 | Ω | |
| Output low | I(PWRGD) = 2.5 mA | 0.2 | 0.3 | V | |
| Minimum VIN for valid output | V(PWRGD) < 0.5 V at 100 µA | 1.2 | 1.5 | V | |