ZHCSCI5B May 2014 – July 2016 TPS544B20 , TPS544C20
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Device Comparison Table
- 6 Pin Configuration and Functions
- 7 Specifications
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 Turn-On and Turn-Off Delay and Sequencing
- 8.3.2 Pre-Biased Output Start-Up
- 8.3.3 Voltage Reference
- 8.3.4 Differential Remote Sense and Output Voltage Setting
- 8.3.5 PMBus Output Voltage Adjustment
- 8.3.6 Switching Frequency
- 8.3.7 Soft-Start
- 8.3.8 Linear Regulators BP3 and BP6
- 8.3.9 External Bypass (BPEXT)
- 8.3.10 Current Monitoring and Low-Side MOSFET Overcurrent Protection
- 8.3.11 High-Side MOSFET Short-Circuit Protection
- 8.3.12 Over-Temperature Protection
- 8.3.13 Input Undervoltage Lockout (UVLO)
- 8.3.14 Output Overvoltage and Undervoltage Protection
- 8.3.15 Fault Protection Responses
- 8.3.16 PMBus General Description
- 8.3.17 PMBus Address
- 8.3.18 PMBus Connections
- 8.3.19 Auto ARA (Alert Response Address) Response
- 8.4 Device Functional Modes
- 8.5 Programming
- 8.6
Register Maps
- 8.6.1 OPERATION (01h)
- 8.6.2 ON_OFF_CONFIG (02h)
- 8.6.3 CLEAR_FAULTS (03h)
- 8.6.4 WRITE_PROTECT (10h)
- 8.6.5 STORE_USER_ALL (15h)
- 8.6.6 RESTORE_USER_ALL (16h)
- 8.6.7 CAPABILITY (19h)
- 8.6.8 VOUT_MODE (20h)
- 8.6.9 VIN_ON (35h)
- 8.6.10 VIN_OFF (36h)
- 8.6.11 IOUT_CAL_OFFSET (39h)
- 8.6.12 IOUT_OC_FAULT_LIMIT (46h)
- 8.6.13 IOUT_OC_FAULT_RESPONSE (47h)
- 8.6.14 IOUT_OC_WARN_LIMIT (4Ah)
- 8.6.15 OT_FAULT_LIMIT (4Fh)
- 8.6.16 OT_WARN_LIMIT (51h)
- 8.6.17 TON_RISE (61h)
- 8.6.18 STATUS_BYTE (78h)
- 8.6.19 STATUS_WORD (79h)
- 8.6.20 STATUS_VOUT (7Ah)
- 8.6.21 STATUS_IOUT (7Bh)
- 8.6.22 STATUS_TEMPERATURE (7Dh)
- 8.6.23 STATUS_CML (7Eh)
- 8.6.24 STATUS_MFR_SPECIFIC (80h)
- 8.6.25 READ_VOUT (8Bh)
- 8.6.26 READ_IOUT (8Ch)
- 8.6.27 READ_TEMPERATURE_2 (8Eh)
- 8.6.28 PMBUS_REVISION (98h)
- 8.6.29 MFR_SPECIFIC_00 (D0h)
- 8.6.30 VREF_TRIM (MFR_SPECIFIC_04) (D4h)
- 8.6.31 STEP_VREF_MARGIN_HIGH (MFR_SPECIFIC_05) (D5h)
- 8.6.32 STEP_VREF_MARGIN_LOW (MFR_SPECIFIC_06) (D6h)
- 8.6.33 PCT_VOUT_FAULT_PG_LIMIT (MFR_SPECIFIC_07) (D7h)
- 8.6.34 SEQUENCE_TON_TOFF_DELAY (MFR_SPECIFIC_08) (D8h)
- 8.6.35 OPTIONS (MFR_SPECIFIC_21) (E5h)
- 8.6.36 MASK_SMBALERT (MFR_SPECIFIC_23) (E7h)
- 8.6.37 DEVICE_CODE (MFR_SPECIFIC_44) (FCh)
-
9 Applications and Implementation
- 9.1 Application Information
- 9.2
Typical Application
- 9.2.1 Design Requirements
- 9.2.2
Detailed Design Procedure
- 9.2.2.1 Switching Frequency Selection
- 9.2.2.2 Inductor Selection
- 9.2.2.3 Output Capacitor Selection
- 9.2.2.4 D-CAP Mode and D-CAP2 Mode Stability
- 9.2.2.5 Input Capacitor Selection
- 9.2.2.6 Bootstrap Capacitor and Resistor Selection
- 9.2.2.7 BP6, BP3 and BPEXT
- 9.2.2.8 R-C Snubber and VIN Pin High-Frequency Bypass
- 9.2.2.9 Temperature Sensor
- 9.2.2.10 Key PMBus Parameter Selection
- 9.2.2.11 Output Voltage Setting and Frequency Compensation Selection
- 9.2.3 Application Curves
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
6 Pin Configuration and Functions
RVF Package
40-Pin LQFN with Thermal Tab
(TOP VIEW)
Pin Functions
| PIN | I/O(1) | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| ADDR0 | 3 | O | Sets low order 3-bits of the PMBus address. Connect a resistor from this pin to AGND. |
| ADDR1 | 2 | O | Sets high order 3-bits of the PMBus address. Connect a resistor from this pin to AGND. |
| AGNDSNS | 13 | G | Analog ground sense. Provides Kelvin connection point to analog ground for precise current measurement. AGNDSNS is internally connected to the thermal tab. Do not connect to the thermal tab externally. Kelvin connect back to AGND pin with a low impedance, low noise path. This kelvin connection serves as the only connection between AGND and GND. |
| AGND | 38 | G | Analog ground return for control circuitry. AGND should not be connected to the exposed thermal pad, GND or PGND, but should be Kelvin connected to the AGNDSNS pin. |
| BP3 | 27 | S | Output of the 3.3-V on-board regulator. This regulator powers the controller and should be bypassed with a minimum of 100-nF capacitor to AGND. |
| BP6 | 28 | S | Output of the 6-V on-board regulator. This regulator powers the driver stage of the controller and should be bypassed with a 4.7-µF ceramic capacitor to GND. |
| BOOT | 7 | S | Bootstrap pin for the internal flying high-side driver. Connect a typical 100-nF capacitor from this pin to the SW pins. |
| BPEXT | 30 | I | External BP voltage for BP crossover function. Bypass with a 4.7-µF ceramic capacitor to GND if used.. Connect to GND if not used. |
| CLK | 5 | I | PMBus CLK pin. See PMBus specification. |
| CNTL | 1 | I | PMBus CNTL pin. See PMBus specification. |
| COMP | 35 | O | Output of the error amplifier. This regulates the D-CAP and D-CAP2 valley voltage reference for output regulation and should be bypassed with a 10-nF capacitor to AGND. |
| DATA | 4 | I/O | PMBus DATA pin. See PMBus specification. |
| DIFFO | 33 | O | Output of the differential sense amplifier. |
| FB | 34 | I | Feedback pin for the control loop. Regulates to a nominal 600 mV if there is no trim applied to the device using VREF_TRIM. |
| GND | 14 | G | Power stage ground return. |
| 15 | |||
| 16 | |||
| 17 | |||
| 18 | |||
| 19 | |||
| 20 | |||
| PGND | 26 | G | Power ground return for controller device. Connect to GND at the thermal tab with a minimum 8 mil wide PCB trace |
| PGOOD | 36 | O | Power good output. Open drain output that floats up when the device is operating and in regulation. Any fault condition causes this pin to pull low. |
| RT | 40 | O | Frequency-setting resistor. Connect a resistor from this pin to AGND to program the switching frequency. |
| SMBALERT | 6 | O | SMBus alert pin. See SMBus specification. |
| SW | 8 | O | Switched power output of the device. Connect the output averaging filter and bootstrap capacitor to this group of pins. |
| 9 | |||
| 10 | |||
| 11 | |||
| 12 | |||
| MODE | 39 | I | D-CAP and D-CAP2 control mode selection pin. Connect to BP3 for D-CAP2 mode control. Connect to AGND for D-CAP mode control. |
| TSNS | 37 | O | External temperature sense signal input. TSNS can be connected to AGND to disable external temperature measurement. |
| VDD | 29 | I | Input Voltage for analog control circuitry. Bypass with a 0.1-µF to 1.0-µF capacitor to GND (thermal pad or GND pins) or through a dedicated connection to AGNDSNS. The VDD voltage is also used for input feed-forward, ON-time generation and High Side Over Current (HSOC). VIN and VDD must be at the same voltage for accurate short circuit protection. |
| VIN | 21 | I | Input power to the power stage. Bypass High-Frequency bypassing with multiple ceramic capacitors to GND is critical. See Layout Recommendations |
| 22 | |||
| 23 | |||
| 24 | |||
| 25 | |||
| VOUTS+ | 31 | I | Output voltage sensing, positive side. This sensing provides remote sensing for PMBus reporting and the voltage control loop. Connect to VOUT at desried regulation point through < 100-Ω resistor. Route with GND to VOUT- using coupled differential pair PCB routing. |
| VOUTS– | 32 | I | Output voltage sensing, negative or common side. This sensing provides remote sensing for PMBus reporting and the voltage control loop. Connect to Ground at desried regulation point through < 100-Ω resistor. Route with VOUT to VOUT+ using coupled differential pair PCB routing. |
| Thermal tab | Package thermal tab. Connect to GND. The thermal tab must have adequate solder coverage for proper operation. | ||
(1) I = Input, O = Output, P = Supply, G = Ground