8.2.2.10 Step 10: Select Loop Compensation Components

There are several industry techniques used to compensate DC/DC regulators. The method presented here is easy to calculate and yields high phase margins. For most conditions, the regulator has a phase margin between 60 and 90 degrees. The method presented here ignores the effects of the slope compensation that is internal to the TPS54218. Because the slope compensation is ignored, the actual crossover frequency is usually lower than the crossover frequency used in the calculations.

To get started, the modulator pole, f_P(mod), and the esr zero, f_Z1 must be calculated using Equation 37 and Equation 38. For C_OUT, derating the capacitor is not needed as the 1.8 V output is a small percentage of the 10 V capacitor rating. If the output is a high percentage of the capacitor rating, use the capacitor manufacturer information to derate the capacitor value. Use Equation 39 and Equation 40 to estimate a starting point for the crossover frequency, f_C. For the example design, f_P(mod) is 4.02 kHz and f_Z1 is 1206 kHz. Equation 39 is the geometric mean of the modulator pole and the esr zero and Equation 40 is the mean of modulator pole and the switching frequency. Equation 39 yields 69.6 kHz and Equation 40 gives 44.8 kHz. Use the lower value of Equation 39 or Equation 40 as the maximum crossover frequency. For this example, fc is 45 kHz. Next, the compensation components are calculated. A resistor in series with a capacitor is used to create a compensating zero. A capacitor in parallel to these two components forms the compensating pole (if needed).

Equation 37.

Equation 38.

Equation 39.

Equation 40.

The compensation design takes the following steps:

1. Set up the anticipated cross-over frequency. Use Equation 41 to calculate the compensation network’s resistor value. In this example, the anticipated cross-over frequency f_C is 45 kHz. The power stage gain (g_M(ps)) is 13 A/V and the error amplifier gain (g_M(ea)) is 225uA/V.
Equation 41.
2. Place compensation zero at the pole formed by the load resistor and the output capacitor. The compensation network’s capacitor can be calculated from Equation 42.
Equation 42.
3. An additional pole can be added to attenuate high frequency noise. In this application, it is not necessary to add it.

From the procedures above, start with a 14.3 kΩ resistor and a 4130pF capacitor. After prototyping and bode plot measurement, the optimized compensation network selected for this design includes a 9.53 kΩ resistor and a 3900 pFΩ capacitor.