ZHCSI10E September 2009 – September 2018 TPS54218
PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 Fixed Frequency PWM Control
- 7.3.2 Slope Compensation and Output Current
- 7.3.3 Bootstrap Voltage (Boot) and Low Dropout Operation
- 7.3.4 Error Amplifier
- 7.3.5 Voltage Reference
- 7.3.6 Adjusting the Output Voltage
- 7.3.7 Enable and Adjusting Undervoltage Lockout
- 7.3.8 Soft-Start Pin
- 7.3.9 Sequencing
- 7.3.10 Constant Switching Frequency and Timing Resistor (RT/CLK Pin)
- 7.3.11 Overcurrent Protection
- 7.3.12 Frequency Shift
- 7.3.13 Reverse Overcurrent Protection
- 7.3.14 Synchronize Using the RT/CLK Pin
- 7.3.15 Power Good (PWRGD Pin)
- 7.3.16 Overvoltage Transient Protection
- 7.3.17 Thermal Shutdown
- 7.4 Device Functional Modes
-
8 Application and Implementation
- 8.1 Application Information
- 8.2
Typical Application
- 8.2.1 Design Requirements
- 8.2.2
Detailed Design Procedure
- 8.2.2.1 Step One: Select the Switching Frequency
- 8.2.2.2 Step Two: Select the Output Inductor
- 8.2.2.3 Step Three: Choose the Output Capacitor
- 8.2.2.4 Step Four: Select the Input Capacitor
- 8.2.2.5 Step Five: Minimum Load DC COMP Voltage
- 8.2.2.6 Step Six: Choose the Soft-Start Capacitor
- 8.2.2.7 Step Seven: Select the Bootstrap Capacitor
- 8.2.2.8 Step Eight: Undervoltage Lockout Threshold
- 8.2.2.9 Step Nine: Select Output Voltage and Feedback Resistors
- 8.2.2.10 Step 10: Select Loop Compensation Components
- 8.2.2.11 Power Dissipation Estimate
- 8.2.3 Application Curves
- 9 Power Supply Recommendations
- 10Layout
- 11器件和文檔支持
- 12機(jī)械、封裝和可訂購信息
封裝選項
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTE|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- RTE|16
訂購信息
7.4.1 Small Signal Model for Loop Response
Figure 31 shows an equivalent model for the TPS54218 device control loop which can be modeled in a circuit simulation program to check frequency response and dynamic load response. The error amplifier is a transconductance amplifier with a gM of 225 μA/V. The error amplifier can be modeled using an ideal voltage controlled current source. The resistor ROUT(ea) and capacitor COUT(ea) model the open loop gain and frequency response of the amplifier. The 1-mV AC voltage source between the nodes a and b effectively breaks the control loop for the frequency response measurements. Plotting a/c shows the small signal response of the frequency compensation. Plotting a/b shows the small signal response of the overall loop. The dynamic loop response can be checked by replacing the RLOAD with a current source with the appropriate load step amplitude and step rate in a time domain analysis.
Figure 31. Small Signal Model for Loop Response