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ZHCSEM8 January 2016 TPS50601-SP

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

HKH|20
- MCDF004D
KGD|0

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsem8_oa

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN	–0.3	7	V
	PVIN	–0.3	7
	EN	–0.3	5.5
	BOOT	–0.3	14
	VSENSE	–0.3	3.3
	COMP	–0.3	3.3
	PWRGD	–0.3	5.5
	SS/TR	–0.3	5.5
	SYNC	–0.3	7
Output voltage	BOOT-PH	0	7	V
	PH	–1	7
	PH 10-ns transient	–3	7
Vdiff	(GND to exposed thermal pad)	–0.2	0.2	V
Output current			6	A
Source current	PH	Current limit		A
Source current	RT		±100	µA
Sink current	PH	Current limit		A
	PVIN	Current limit		A
	COMP		±200	µA
	PWRGD	–0.1	5	mA
Operating junction temperature		–55	150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
T_J	Junction operating temperature range		–55		125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS50601-SP	UNIT
		HKH (CFP)
		20 PINS
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.514	°C/W

(1) Taken per Mil Standard 883 method 1012.1

7.5 Electrical Characteristics

T_J = –55°C to 125°C, V_IN = 3 V to 6.3 V, P_VIN = 1.6 V to 6.3 V (unless otherwise noted)

PARAMETER	TEST CONDITIONS		MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage			1.6		6.3	V
VIN operating input voltage			3		6.3	V
VIN internal UVLO threshold	V_IN rising			2.75	3	V
VIN internal UVLO hysteresis				50		mV
VIN shutdown supply current	V_EN = 0 V			2.5	5.9	mA
VIN operating – non switching supply current	V_SENSE = V_BG			5	10	mA
ENABLE AND UVLO (EN PIN)
Enable threshold	Rising			1.13	1.18	V
Enable threshold	Falling		1.05	1.09		V
Input current	V_EN = 1.1 V			3.2		μA
Hysteresis current	V_EN = 1.3 V			3		μA
VOLTAGE REFERENCE
Voltage reference	0 A ≤ Iout ≤ 6 A	–55°C	0.767	0.795	0.804	V
		25°C	0.785	0.795	0.804
		125°C	0.785	0.795	0.815
MOSFET
High-side switch resistance	BOOT-PH = 2.2 V			55		mΩ
High-side switch resistance⁽¹⁾	BOOT-PH = 6.3 V			50		mΩ
Low-side switch resistance⁽¹⁾	V_IN = 6.3 V			50		mΩ
ERROR AMPLIFIER
Error amplifier transconductance (g_m)⁽²⁾	–2 μA < I_COMP < 2 μA, V_(COMP) = 1 V			1300		μS
Error amplifier dc gain⁽²⁾	V_SENSE = 0.792 V			39000		V/V
Error amplifier source/sink⁽²⁾	V_(COMP) = 1 V, 40-mV input overdrive			±125		μA
Start switching threshold⁽²⁾				0.25		V
COMP to Iswitch gm⁽²⁾				18		A/V
CURRENT LIMIT
High-side switch current limit threshold ⁽³⁾	V_IN = 6.3 V		8	11		A
Low-side switch sourcing current limit⁽³⁾	V_IN = 6.3 V		7	10		A
Low-side switch sinking current limit	V_IN = 6.3 V			3		A
THERMAL SHUTDOWN
Thermal shutdown				175		°C
Thermal shutdown hysteresis				10		°C
INTERNAL SWITCHING FREQUENCY
Internally set frequency	RT = Open		395	500	585	kHz
Externally set frequency	RT = 100 kΩ (1%)			480		kHz
	RT = 485 kΩ (1%)			100
	RT = 47 kΩ (1%)			1000
EXTERNAL SYNCHRONIZATION
SYNC out low-to-high rise time (10%/90%)	Cload = 25 pF			25	111	ns
SYNC out high-to-low fall time (90%/10%)	Cload = 25 pF			3	15	ns
Falling edge delay time⁽⁵⁾				180		°
SYNC out high level threshold	I_OH = 50 µA		2			V
SYNC out low level threshold	I_OL = 50 µA				600	mV
SYNC in low level threshold			800			mV
SYNC in high level threshold					1.85	V
SYNC in frequency range⁽⁴⁾	Percent of program frequency		–5%		5%
SYNC in frequency range⁽⁴⁾			100		1000	kHz
PH (PH PIN)
Minimum on time	Measured at 10% to 90% of VIN, 25°C, I_PH = 2 A			94	175	ns
Minimum off time	BOOT-PH ≥ 3 V			500		ns
BOOT (BOOT PIN)
BOOT-PH UVLO				2.2	3	V
SLOW START AND TRACKING (SS/TR PIN)
SS charge current				2.5		μA
SS/TR to VSENSE matching	V_(SS/TR) = 0.4 V			30	90	mV
POWER GOOD (PWRGD PIN)
VSENSE threshold	V_SENSE falling (fault)			91		% Vref
	V_SENSE rising (good)			94		% Vref
	V_SENSE rising (fault)			109		% Vref
	V_SENSE falling (good)			106		% Vref
Output high leakage	V_SENSE = Vref, V(PWRGD) = 5 V			30	181	nA
Output low	I_(PWRGD) = 2 mA				0.3	V
Minimum VIN for valid output	V_(PWRGD) < 0.5 V at 100 μA			0.6	1	V
Minimum SS/TR voltage for PWRGD					1.4	V

(1) Measured at pins

(2) Ensured by design only. Not tested in production.

(3) Parameter is not tested in production.

(4) Parameter is production tested at nominal voltage with V_IN = P_VIN = 5V.

(5) Bench verified. Not tested in production.

7.6 Dissipation Ratings

See ⁽¹⁾⁽²⁾⁽³⁾⁽⁴⁾

PACKAGE	R_θJA THERMAL IMPEDANCE, JUNCTION TO AMBIENT	R_θJCTHERMAL IMPEDANCE, JUNCTION TO CASE (THERMAL PAD)	R_θJB THERMAL IMPEDANCE, JUNCTION TO BOARD
HKH	39.9°C/W	0.52°C/W	43.1°C/W

(1) Maximum power dissipation may be limited by overcurrent protection

(2) Power rating at a specific ambient temperature, T_A, should be determined with a junction temperature of 150°C. This is the point where distortion starts to substantially increase. Thermal management of the PCB should strive to keep the junction temperature at or below 150°C for best performance and long-term reliability. See power dissipation estimate in Application and Implementation for more information.

(3) Test board conditions:

2.5 inches × 2.5 inches, 4 layers, thickness: 0.062 inch
2-oz. copper traces located on the top of the PCB
2-oz. copper ground planes on the 2 internal layers and bottom layer
40.010-inch thermal vias located under the device package

(4) For information on thermal characteristics, see SPRA953.

A. See data sheet for absolute maximum and minimum recommended operating conditions.

B. Product operating life design goal is >15 years for 65°C ≤ T_J ≤ 95°C based on silicon technology characterization per MIL-PRF-38535.

C. The predicted operating lifetime versus junction temperature is based on reliability modeling using electromigration as the dominant failure mechanism affecting device wearout for the specific device process and design characteristics.

Figure 1. 6-A Continuous Current Estimated Device Life