久久国产亚洲高清观看5388,国产精品αv在线观看,久久国产精品偷导航

ZHCSAP1D December 2012 – September 2014 TPS43060 , TPS43061

PRODUCTION DATA.

封裝選項

機械數(shù)據(jù) (封裝 | 引腳)

RTE|16
- MPQF149D

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

RTE|16
- QFND414C

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature (unless otherwise noted)

		MIN	MAX	UNIT
Voltage	Input: VIN, EN, ISNS+, ISNS–	–0.3	40	V
	DC voltage: SW	–0.6	60	V
	Transient voltage (10 ns max): SW	–2	60	V
	FB, RT/CLK, COMP, SS	–0.3	3.6	V
	BOOT, HDRV voltage with respect to ground		65	V
	BOOT, HDRV voltage with respect to SW pin		8	V
	VCC, PGOOD, LDRV	–0.3	8	V
Operating junction temperature		–40	150	°C

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	–2000	2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	–500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage range	4.5	38	V
V_OUT	Output voltage range	V_IN	58	V
V_EN	EN voltage range	0	38	V
V_CLK	External switching frequency logic input range	0	3.6	V
T_J	Operating junction temperature	–40	150	°C

7.4 Thermal Characteristics

over operating free-air temperature range (unless otherwise noted)

THERMAL METRIC ⁽¹⁾		WQFN (16-PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	65.7	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	42.3
R_θJB	Junction-to-board thermal resistance	18
ψ_JT	Junction-to-top characterization parameter	0.9
ψ_JB	Junction-to-board characterization parameter	17.9
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	22.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

V_IN = 4.5 to 38 V, T_J = –40ºC to 150ºC, unless otherwise noted. Typical values are at T_A = 25ºC

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY AND ENABLE
V_IN	Input voltage range			4.5		38	V
V_UV	Input undervoltage threshold		V_IN falling	3.7	3.9	4	V
V_UV	Input undervoltage threshold		V_IN rising	3.9	4.1	4.3	V
V_hys	Undervoltage lockout hysteresis				200		mV
I_Q	Operating quiescent current into V_IN		Device non-switching, R_T = 115 kΩ, V_FB = 2 V		600	800	µA
I_SD	Shutdown current		V_EN = 0.4 V		1.5	5	µA
V_EN	EN pin voltage threshold to standby		V_EN ramping down	0.4	0.7	0.9	V
	EN pin voltage threshold to enable the device		V_EN ramping up	1.12	1.21	1.29	V
	EN pin voltage threshold to disable the device		V_EN ramping down	1	1.14	1.28	V
I_EN	EN pin pullup current		V_EN = 1 V		1.8		µA
I_EN	EN pin hysteresis current		V_EN= 1.3 V		3.2	4.6	µA
t_EN	EN to start switching time		C_VCC = 0.47 µF		125		µs
V_CC	V_CC voltage	TPS43060	V_IN = 12 to 38 V, I_VCC = 0 µA		7.5		V
		TPS43060	V_IN = 4.5 V, I_VCC = 0 µA		4.5		V
		TPS43061	V_IN = 12 to 38 V, I_VCC = 0 µA		5.5		V
		TPS43061	V_IN = 4.5 V, I_VCC = 0 µA		4.5		V
I_VCC	V_CC pin maximum output current			50			mA
VOLTAGE REFERENCE AND ERROR AMPLIFIER
V_REF	Feedback voltage reference		T_J = 25°C	1.21	1.22	1.23	V
V_REF	Feedback voltage reference		T_J = –40°C to 150°C	1.195	1.22	1.244
I_FB	Error amplifier input bias current				20		nA
I_COMP	COMP pin sink current		V_FB = V_REF + 250 mV, V_COMP = 1.5 V		160		µA
I_COMP	COMP pin source current		V_FB = V_REF – 250 mV, V_COMP = 1.5 V		160		µA
V_CLAMP	COMP pin clamp voltage		High clamp, V_FB = 1 V		2.1		V
	COMP pin clamp voltage		Low clamp, V_FB = 1.5 V		0.7
	COMP pin threshold		Duty cycle = 0%		1		V
G_ea	Error amplifier transconductance				1.1		mS
R_ea	Error amplifier output resistance				10		MΩ
F_ea	Error amplifier crossover frequency				2		MHz
CURRENT SENSE
V_CSmax	Maximum current sense threshold		At 0% duty cycle	64	73	82	mV
V_CSmax	Maximum current sense threshold		At max duty cycle	50	61	72	mV
V_RCsns	Reverse current sense threshold				3.8		mV
I_SNS+	Sense+ pin current				70		µA
I_SNS–	Sense– pin current				70		µA
RT/CLK
ƒ_SW	Switching frequency		Operating frequency range using resistor timing mode	50		1000	kHz
			R_T = 115 kΩ	450	500	550	kHz
			R_T = 75 kΩ	675	750	825	kHz
V_RT/CLK	RT/CLK pin voltage				0.5		V
t_CLK-min	Minimum input clock pulse duration		P_LL = 500 kHz		14	60	ns
v_CLK-H	RT/CLK high threshold				1.78	2	V
ƒ_CLK	RT/CLK low threshold			0.4	1.35		V
ƒ_CLK	PLL frequency sync range			300		1000	kHz
t_PLLIN	PLL lock in time				100	250	µs
t_PLLEXIT	Last RT/CLK falling edge to return to resistor timing mode if CLK is not present				140	250	µs
POWER SWITCH DRIVERS
R_LDRV	LDRV pullup resistance	TPS43060	V_IN = 12 to 40 V		2		Ω
		TPS43060	V_IN = 4.5 V		3		Ω
		TPS43061	V_IN = 12 to 40 V		2.5		Ω
		TPS43061	V_IN = 4.5 V		3		Ω
	LDRV pulldown resistance	TPS43060	V_IN = 12 to 40 V		1.2		Ω
		TPS43060	V_IN = 4.5 V		2		Ω
		TPS43061	V_IN = 12 to 40 V		1.6		Ω
		TPS43061	V_IN = 4.5 V		2		Ω
R_HDRV	HDRV pullup resistance	TPS43060	V_IN = 12 to 40 V		2		Ω
		TPS43060	V_IN = 4.5 V		2.8		Ω
		TPS43061	V_IN = 12 to 40 V		5		Ω
		TPS43061	V_IN = 4.5 V		5.5		Ω
	HDRV pulldown resistance	TPS43060	V_IN = 12 to 40 V		1.2		Ω
		TPS43060	V_IN = 4.5 V		1.9		Ω
		TPS43061	V_IN = 12 to 40 V		3		Ω
		TPS43061	V_IN = 4.5 V		3.7		Ω
t_HR	High-side gate rise time, 10% to 90%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_HR	High-side gate rise time, 10% to 90%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		20		ns
t_HF	High-side gate fall time, 90% to 10%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		10		ns
t_HF	High-side gate fall time, 90% to 10%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_LR	Low-side gate rise time, 10% to 90%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
t_LR	Low-side gate rise time, 10% to 90%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		20		ns
t_LF	Low-side gate fall time, 90% to 10%	TPS43060	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		10		ns
t_LF	Low-side gate fall time, 90% to 10%	TPS43061	C_LOAD = 2.2 nF, V_IN = 12 to 40 V		15		ns
V_F	BOOT diode forward voltage drop	TPS43061	I_F = 10 mA, T_A = 25ºC		0.75		V
I_BOOT	BOOT pin leakage current	TPS43061	V_r = 60 V		0.1		µA
t_ON	LDRV minimum on pulse duration		ƒ_SW = 500 kHz		100		ns
t_OFF	LDRV minimum off pulse duration		ƒ_SW = 500 kHz		250		ns
t_delay	Time delay between LDRV fall(50%) to HDRV rise (50%), t_non-overlap1	TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
	Time delay between HDRV fall (50%) to LDRV rise (50%), t_non-overlap2	TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43060, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 12 V		65		ns
		TPS43061, C_LOAD = open, ƒ_SW = 500 kHz	V_IN = 4.5 V		75		ns
POWER GOOD, SS AND OVP
P_GDL	PGOOD low threshold		V_FB with respect to feedback voltage reference, V_FB falling	86%	90%	93%
P_GDL	PGOOD low hysteresis		V_FB with respect to feedback voltage reference		2%
P_GDH	PGOOD high threshold		V_FB with respect to feedback voltage reference, V_FB rising	107%	110%	114%
P_GDH	PGOOD high hysteresis		V_FB with respect to feedback voltage reference		2%
P_GDSC	PGOOD sink current		V_PGOOD = 0.4 V	1.8	4		mA
P_GDLK	PGOOD pin leakage current		V_PGOOD = 7 V		100		nA
V_{IN_PGD}	Minimum V_IN for valid PGOOD				2.5	4.3	V
I_SS	Soft-start bias current		V_SS = 0 V		5		µA
R_SS	Soft-start discharge resistance				250		Ω
V_OVP	OVP threshold		V_FB with respect to feedback voltage reference, V_FB rising	104%	107%	110%
V_OVP	OVP hysteresis		V_FB with respect to feedback voltage reference		2%
THERMAL SHUTDOWN
T_SD	Thermal shutdown set threshold				165		°C
T_hyst	Thermal shutdown hysteresis				15		°C