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SLUS772G March 2008 – June 2020 TPS40210 , TPS40211

PRODUCTION DATA

封裝選項

請參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。

機械數(shù)據(jù) (封裝 | 引腳)

DRC|10
DGQ|10

散熱焊盤機械數(shù)據(jù) (封裝 | 引腳)

訂購信息

6.5 Electrical Characteristics

T_J = –40°C to 125°C, V_DD= 12V_dc, all parameters at zero power dissipation (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
VOLTAGE REFERENCE
V_FB	Feedback voltage range	TPS40210	COMP = FB, 4.5 ≤ V_DD ≤ 52 V, T_J = 25°C	693	700	707	mV
	Feedback voltage range	TPS40211	COMP=FB, 4.5 ≤ V_DD ≤ 52 V, T_J = 25°C	254	260	266
		TPS40210	COMP = FB, 4.5 ≤ V_DD ≤ 52 V, -40°C ≤ T_J ≤ 125°C	686	700	714
		TPS40211	COMP = FB, 4.5 ≤ V_DD ≤ 52 V, -40°C ≤ T_J ≤ 125°C	250	260	270
INPUT SUPPLY
V_DD	Input voltage range			4.5		52	V
I_DD	Operating current		4.5 ≤ V_DD ≤ 52 V, no switching, V_DIS < 0.8		1.5	2.5	mA
			2.5 ≤ V_DIS ≤ 7 V		10	20	μA
			V_DD < V_UVLO(on), V_DIS < 0.8			530	μA
UNDERVOLTAGE LOCKOUT
V_UVLO(on)	Turn on threshold voltage			4.00	4.25	4.50	V
V_UVLO(hyst)	UVLO hysteresis			140	195	240	mV
OSCILLATOR
f_OSC	Oscillator frequency range⁽¹⁾			35		1000	kHz
f_OSC	Oscillator frequency		R_RC = 182 k?, C_RC = 330 pF	260	300	340	kHz
	Frequency line regulation		4.5 ≤ V_DD ≤ 52 V	-20%		7%
V_SLP	Slope compensation ramp			520	620	720	mV
PWM
t_ON(min)	Minimum pulse width		V_DD = 12 V⁽¹⁾		275	400	ns
t_ON(min)	Minimum pulse width		V_DD = 30 V		90	200
t_OFF(min)	Minimum off time				170	200
V_VLY	Valley voltage				1.2		V
SOFT-START
V_SS(ofst)	Offset voltage from SS pin to error amplifier input				700		mV
R_SS(chg)	Soft-start charge resistance			320	430	600	k?
R_SS(dchg)	Soft-start discharge resistance			840	1200	1600	k?
ERROR AMPLIFIER
GBWP	Unity gain bandwidth product⁽¹⁾			1.5	3.0		MHz
A_OL	Open loop gain⁽¹⁾			60	80		dB
I_IB(FB)	Input bias current (current out of FB pin)				100	300	nA
I_COMP(src)	Output source current		V_FB = 0.6 V, V_COMP = 1 V	100	250		μA
I_COMP(snk)	Output sink current		V_FB = 1.2 V, V_COMP = 1 V	1.2	2.5		mA
OVERCURRENT PROTECTION
V_ISNS(oc)	Overcurrent detection threshold (at ISNS pin)		4.5 ≤ V_DD < 52 V, -40°C ≤ T_J ≤ 125°C	120	150	180	mV
D_OC	Overcurrent duty cycle⁽¹⁾					2%
V_SS(rst)	Overcurrent reset threshold voltage (at SS pin)			100	150	350	mV
T_BLNK	Leading edge blanking⁽¹⁾				75		ns
CURRENT SENSE AMPLIFIER
A_CS	Current sense amplifier gain			4..2	5.6	7.2	V/V
I_B(ISNS)	Input bias current				1	3	μA
DRIVER
I_GDRV(src)	Gate driver source current		V_GDRV = 4 V, T_J = 25°C	375	400		mA
I_GDRV(snk)	Gate driver sink current		V_GDRV = 4 V, T_J = 25°C	330	400		mA
LINEAR REGULATOR
V_BP	Bypass voltage output		0 mA < I_BP < 15 mA	7	8	9	V
DISABLE/ENABLE
V_DIS(en)	Turn-on voltage			0.7		1.3	V
V_DIS(hys)	Hysteresis voltage			25	130	220	mV
R_DIS	DIS pin pulldown resistance			0.7	1.1	1.5	M?

(1) Ensured by design. Not production tested.