ZHCSIV9F September 2009 – October 2018 TPS386000 , TPS386040
PRODUCTION DATA.
5 Pin Configuration and Functions
RGP Package
20-Pin VQFN
Top View
Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | NO. | |||
| VDD | 14 | I | Supply voltage. TI recommends connecting a 0.1-μF ceramic capacitor close to this pin. | |
| GND | 12 | — | Ground | |
| SENSE1 | 10 | I | Monitor voltage input to SVS-1 | When the voltage at this terminal drops below the threshold voltage (VITN), RESET1 is asserted. |
| SENSE2 | 9 | I | Monitor voltage input to SVS-2 | When the voltage at this terminal drops below the threshold voltage (VITN), RESET2 is asserted. |
| SENSE3 | 8 | I | Monitor voltage input to SVS-3 | When the voltage at this terminal drops below the threshold voltage (VITN), RESET3 is asserted. |
| SENSE4L | 7 | I | Falling monitor voltage input to SVS-4. When the voltage at this terminal drops below the threshold voltage (VITN), RESET4 is asserted. | |
| SENSE4H | 6 | I | Rising monitor voltage input to SVS-4. When the voltage at this terminal exceeds the threshold voltage (VITP), RESET4 is asserted. This pin can also be used to monitor the negative voltage rail in combination with VREF pin. Connect to GND if not being used. | |
| CT1 | 5 | — | Reset delay programming pin for SVS-1 | Connecting this pin to VDD through a 40-kΩ to
200-kΩ resistor, or leaving it open, selects a fixed delay time (see the Electrical Characteristics). Connecting a capacitor > 220 pF between this pin and GND selects the programmable delay time (see the Reset Delay Time section). |
| CT2 | 4 | — | Reset delay programming pin for SVS-2 | |
| CT3 | 3 | — | Reset delay programming pin for SVS-3 | |
| CT4 | 2 | — | Reset delay programming pin for SVS-4 | |
| VREF | 13 | O | Reference voltage output. By connecting a resistor network between this pin and the negative power rail, SENSE4H can monitor the negative power rail. This pin is intended to only source current into resistor(s). Do not connect resistor(s) to a voltage higher than 1.2 V. Do not connect only a capacitor. | |
| MR | 1 | I | Manual reset input for SVS-1. Logic low level of this pin asserts RESET1. | |
| WDI | 20 | I | Watchdog timer (WDT) trigger input. Inputting either a positive or negative logic edge every
610 ms (typical) prevents WDT time out at the WDO or WDO pin. Timer starts from releasing event of RESET1. |
|
| NC | 11 | — | Not internal connection. TI recommends connecting this pin to the GND pin (pin 12), which is next to this pin. | |
| Thermal Pad | PAD | — | This pad is the IC substrate. This pad must be connected only to GND or to the floating thermal pattern on the printed-circuit board (PCB). | |
| TPS386000 | ||||
| RESET1 | 15 | O | Active low reset output of SVS-1 | RESETn is an open-drain output pin. When RESETn is asserted, this pin remains in a low-impedance state. When RESETn is released, this pin goes to a high-impedance state after the delay time programmed by CTn. A pullup resistor to VDD or another voltage source is required. |
| RESET2 | 16 | O | Active low reset output of SVS-2 | |
| RESET3 | 17 | O | Active low reset output of SVS-3 | |
| RESET4 | 18 | O | Active low reset output of SVS-4 | |
| WDO | 19 | O | Watchdog timer output. This is an open-drain output pin. When WDT times out, this pin goes to a low-impedance state to GND. If there is no WDT time-out, this pin stays in a high-impedance state. | |
| TPS386040 | ||||
| RESET1 | 15 | O | Active low reset output of SVS-1 | RESETn is a push-pull logic buffer output pin. When RESETn is asserted, this pin remains logic low. When RESETn is released, this pin goes to logic high after the delay time programmed by CTn. |
| RESET2 | 16 | O | Active low reset output of SVS-2 | |
| RESET3 | 17 | O | Active low reset output of SVS-3 | |
| RESET4 | 18 | O | Active low reset output of SVS-4 | |
| WDO | 19 | O | Watchdog timer output. This is a push-pull output pin. When WDT times out, this pin goes to logic low. If there is no WDT time-out, this pin stays in logic high. | |