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ZHCSCK2 June 2014

PRODUCTION DATA.

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請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

RVC|20

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

zhcsck2_oa

7 Specifications

7.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted) ⁽¹⁾

		VALUE		UNIT
		MIN	MAX	UNIT
Input voltage range	IN, OUT, PGTH, PGOOD, EN/UVLO, OVP, DEVSLP, FLT	–0.3	20	V
	IN (10 ms Transient)		22
	dVdT, ILIM	–0.3	3.6
	IMON	–0.3	7
Sink current	PGOOD, FLT, dVdT		10	mA
Source current	dVdT, ILIM, IMON	Internally Limited
Maximum junction, T_J		–40	150	°C
Continuous power dissipation		See the Thermal Characteristics

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

7.2 Handling Ratings

			MIN	MAX	UNIT
T_stg	Storage temperature range		–65	150	°C
V_ESD	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	-2	2	kV
V_ESD	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	-500	500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
Input voltage range	IN	2.7		18	V
	EN/UVLO, OVP, DEVSLP, OUT, PGTH, PGOOD, FLT	0		18
	dVdT, ILIM	0		3
	IMON	0		6
Resistance	ILIM	16.9		150	kΩ
Resistance	IMON	1			kΩ
External capacitance	OUT	0.1			µF
External capacitance	dVdT			470	nF
Operating junction temperature range, T_J		–40	25	125	°C

7.4 Thermal Characteristics⁽¹⁾

THERMAL METRIC		TPS25940	UNIT
THERMAL METRIC		RVC (20) PINS	UNIT
R_θJA	Junction-to-ambient thermal resistance	38.1	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance	40.5
R_θJB	Junction-to-board thermal resistance	13.6
ψ_JT	Junction-to-top characterization parameter	0.6
ψ_JB	Junction-to-board characterization parameter	13.7
R_θJCbot	Junction-to-case (bottom) thermal resistance	3.4

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Conditions are –40°C ≤ T_J=T_A ≤ 125°C, 2.7 V ≤ V_(IN) = 18 V, V_(EN_/UVLO) = 2 V, V_(OVP) = V_(DEVSLP) = V_(PGTH) = 0 V, R_(ILIM) = 150 kΩ, C_(OUT) = 1 µF, C_(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. Positive current into terminals. All voltages referenced to GND (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY VOLTAGE AND INTERNAL UNDERVOLTAGE LOCKOUT
V_(IN)	Operating Input Voltage		2.7		18	V
V_(UVR)	Internal UVLO threshold, rising		2.2	2.3	2.4	V
V_(UVRhys)	Internal UVLO hysteresis		105	116	125	mV
I_Q_(ON)	Supply current, Enabled	V_(EN/UVLO) = 2 V, V_(IN) = 3 V	140	210	300	µA
		V_(EN/UVLO) = 2 V, V_(IN) = 12 V	140	199	260
		V_(EN/UVLO) = 2 V, V_(IN) = 18 V	140	202	270
I_Q_(OFF)	Supply current, Disabled	V_(EN/UVLO) = 0 V, V_(IN) = 3 V	4	8.6	15	µA
		V_(EN/UVLO) = 0 V, V_(IN) = 12 V	6	15	20
		V_(EN/UVLO) = 0 V, V_(IN) = 18 V	8	18.5	25
I_Q_(DEVSLP)	Supply current, DevSleep Mode	V_(DEVSLP) = 0 V, V_(IN) = 2.7V to 18V	70	95	130	µA
ENABLE AND UNDERVOLTAGE LOCKOUT (EN/UVLO) INPUT
V_(ENR)	EN/UVLO threshold voltage, rising		0.97	0.99	1.01	V
V_(ENF)	EN/UVLO threshold voltage, falling		0.9	0.92	0.94	V
V_(SHUTF)	EN threshold voltage for Low I_Q shutdown, falling		0.3	0.47	0.63	V
V_(SHUTF_hys)	EN hysteresis for low I_Q shutdown, hysteresis⁽¹⁾			66		mV
I_EN	EN Input leakage current	0 V ≤ V_(EN/UVLO) ≤ 18 V	–100	0	100	nA
OVER VOLTAGE PROTECTION (OVP) INPUT
V_(OVPR)	Overvoltage Threshold Voltage, Rising,		0.97	0.99	1.01	V
V_(OVPF)	Overvoltage Threshold Voltage, Falling		0.9	0.92	0.94	V
I_(OVP)	OVP Input Leakage Current	0 V ≤ V_(OVP) ≤ 5 V	-100	0	100	nA
DEVSLP MODE INPUT (DEVSLP): ACTIVE HIGH
V_(DEVSLPR)	DEVSLP threshold voltage, rising		1.6	1.85	2	V
V_(DEVSLPF)	DEVSLP threshold voltage, falling		0.8	0.96	1.1	V
I_(DEVSLP)	DEVSLP input leakage current	0.2 V ≤ V_(DEVSLP) ≤ 18 V	0.6	1	1.25	µA
OUTPUT RAMP CONTROL (dVdT)
I_(dVdT)	dVdT charging current	V_(dVdT)= 0 V	0.85	1	1.15	µA
R_(dVdT)	dVdT discharging resistance	EN/UVLO = 0 V, I_(dVdT) = 10 mA sinking		16	24	Ω
V_(dVdTmax)	dVdT maximum capacitor voltage		2.6	2.88	3.1	V
GAIN_(dVdT)	dVdT to OUT gain	ΔV_(OUT)/ΔV_(dVdT)	11.65	11.9	12.05	V/V
CURRENT LIMIT PROGRAMMING (ILIM)
V_(ILIM)	ILIM bias voltage			0.87		V
I_(LIM)	Current limit⁽²⁾	R_(ILIM) = 150 kΩ, (V_(IN) - V_(OUT)) = 1 V	0.53	0.58	0.63	A
		R_(ILIM) = 88.7 kΩ, (V_(IN) - V_(OUT)) = 1 V	0.9	0.99	1.07
		R_(ILIM) = 42.2 kΩ, (V_(IN) - V_(OUT)) = 1 V	1.92	2.08	2.25
		R_(ILIM) = 24.9 kΩ, (V_(IN) - V_(OUT)) = 1 V	3.25	3.53	3.81
		R_(ILIM) = 16.9 kΩ, (V_(IN) - V_(OUT)) = 1 V	4.78	5.2	5.62
		R_(ILIM) = OPEN, Open resistor current limit (Single Point Failure Test: UL60950)	0.35	0.45	0.55
		R_(ILIM) = SHORT, Shorted resistor current limit (Single Point Failure Test: UL60950)	0.55	0.67	0.8
I_{(DEVSLP(LIM))}	DevSleep Mode Current Limit		0.55	0.67	0.8	A
I_OS	Short-circuit current limit ⁽²⁾	R_(ILIM) = 42.2 kΩ, V_(VIN) = 12 V, (V_(IN) -V_(OUT)) = 5 V	1.91	2.07	2.24	A
		R_(ILIM) = 24.9 kΩ, V_(VIN) = 12 V, (V_(IN) -V_(OUT)) = 5 V	3.21	3.49	3.77
		R_(ILIM) = 16.9 kΩ, V_(VIN) = 12 V, (V_(IN) -V_(OUT))= 5 V, -40°C ≤ T_J ≤ 85°C	4.7	5.11	5.52
I_(FASTRIP)	Fast-Trip comparator threshold⁽¹⁾⁽²⁾			1.5 x I_(LIM) + 0.375		A
CURRENT MONITOR OUTPUT (IMON)
GAIN_(IMON)	Gain Factor I_(IMON):I_(OUT)	1 A ≤ I_(OUT) ≤ 5 A	47.78	52.3	57.23	µA/A
MOSFET – POWER SWITCH
R_ON	IN to OUT - ON Resistance	1 A ≤ I_(OUT) ≤ 5 A, T_J = 25°C	34	42	49	mΩ
		1 A ≤ I_(OUT) ≤ 5 A, -40°C ≤ T_J ≤ 85°C	26	42	58
		1 A ≤ I_(OUT) ≤ 5 A, -40°C ≤ T_J ≤ 125°C	26	42	64
PASS FET OUTPUT (OUT)
I_lkg(OUT)	OUT leakage current in off state	V_(IN) = 18 V, V_(EN/UVLO) = 0 V, V_(OUT) = 0 V (Sourcing)	–2	0	2	µA
I_lkg(OUT)	OUT leakage current in off state	V_(IN) = 2.7 V, V_(EN/UVLO) = 0 V, V_(OUT) = 18 V (Sinking)	6	13	20	µA
V_(REVTH)	V_(IN) -V_(OUT) threshold for reverse protection comparator, falling		–15	-9.3	–3	mV
V_(FWDTH)	V_(IN) -V_(OUT) threshold for reverse protection comparator, rising		86	100	114	mV
FAULT FLAG (FLT): ACTIVE LOW
R_(FLT)	FLT internal pull-down resistance	V_(OVP) = 2 V, I_(FLT) = 5 mA sinking	10	18	30	Ω
I_(FLT)	FLT input leakage current	0 V ≤ V_(FLT) ≤ 18 V	–1	0	1	µA
POSITIVE INPUT for POWER-GOOD COMPARATOR (PGTH)
V_(PGTHR)	PGTH threshold voltage, rising		0.97	0.99	1.01	V
V_(PGTHF)	PGTH threshold voltage, falling		0.9	0.92	0.94	V
I_(PGTH)	PGTH input leakage current	0 V ≤ V_(PGTH) ≤ 18 V	–100	0	100	nA
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
R_(PGOOD)	PGOOD internal pull-down resistance	V_(PGTH) = 0V, I_(PGOOD)= 5 mA sinking	10	20	35	Ω
I_(PGOOD)	PGOOD input leakage current	0 V ≤ V_(PGOOD) ≤ 18 V	–1	0	1	µA
THERMAL SHUT DOWN (TSD)
T_(TSD)	TSD Threshold⁽¹⁾			160		°C
T_(TSDhys)	TSD Hysteresis⁽¹⁾			12		°C
	Thermal Fault: (Latched or Auto-Retry)	TPS25940L		LATCHED
	Thermal Fault: (Latched or Auto-Retry)	TPS25940A		AUTO-RETRY

(1) These parameters are provided for reference only and do not constitute part of TI's published device specifications for purposes of TI's product warranty.

(2) Pulse-testing techniques maintain junction temperature close to ambient temperature. Thermal effects must be taken into account separately.

7.6 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
ENABLE and UVLO INPUT
t_ON(dly)	EN turn on delay	EN/UVLO ↑ (100mV above V_(ENR)) to V_(OUT) = 100 mV, C_(dVdT) < 0.8 nF		220		µs
t_ON(dly)	EN turn on delay	EN/UVLO ↑ (100mV above V_(ENR)) to V_(OUT) = 100 mV, C_(dVdT) ≥ 0.8 nF, [C_(dVdT) in nF]		100 + 150 x C_(dVdT)		µs
t_OFF(dly)	EN turn off delay	EN/UVLO ↓ (100mV below V_(ENF)) to FLT↓		2		µs
OVERVOLTAGE PROTECTION INPUT (OVP)
t_OVP(dly)	OVP disable delay	OVP↑ (100mV above V_(OVPR)) to FLT↓		2		µs
OUTPUT RAMP CONTROL (dV/dT )
t_dVdT	Output ramp time	EN/UVLO ↑ to V_(OUT)= 4.5 V, with C_(dVdT) = open		0.12		ms
		EN/UVLO ↑ to V_(OUT) = 11 V, with C_(dVdT) = open	0.25	0.37	0.5
		EN/UVLO ↑ to V_(OUT) = 11 V, with C_(dVdT) = 1 nF		0.97
CURRENT LIMIT
t_FASTRIP(dly)	Fast-Trip comparator delay	I_(OUT) > I_(FASTRIP)		200		ns
REVERSE PROTECTION COMPARATOR
t_REV(dly)	Reverse protection comparator delay	(V_(IN) - V_(OUT))↓ (1 mV overdrive below V_(REVTH)) to FLT↓		10		µs
t_REV(dly)		(V_(IN) - V_(OUT))↓ (10 mV overdrive below V_(REVTH)) to FLT↓		1
t_FWD(dly)		(V_(IN) - V_(OUT))↑ (10 mV overdrive above V_(FWDTH)) to FLT↑		3.1
POWER-GOOD COMPARATOR OUTPUT (PGOOD): ACTIVE HIGH
t_PGOODR	PGOOD delay (de-glitch) time	Rising edge	0.42	0.54	0.66	ms
t_PGOODF	PGOOD delay (de-glitch) time	Falling edge	0.42	0.54	0.66	ms
THERMAL SHUT DOWN (TSD)
	Retry delay in TSD	TPS25940A Only		128		ms

7.7 Typical Characteristics

Conditions are –40°C ≤ T_A= T_J ≤ 125°C, V_(IN) = 12 V, V_(EN/UVLO) = 2 V, V_(OVP) = V_(DEVSLP) = V_(PGTH) = 0 V, R_(ILIM) = 150 kΩ, C_(OUT) = 1 µF, C_(dVdT) = OPEN, PGOOD = FLT = IMON = OPEN. (unless stated otherwise)

Figure 1. UVLO Threshold Voltage vs Temperature

Figure 3. Input Supply Current vs Supply Voltage at Shutdown

Figure 5. EN Threshold Voltage vs Temperature

Figure 7. PGTH Threshold Voltage vs Temperature

Figure 9. Enable Turn ON Delay vs Temperature

Figure 11. OVP Disable Delay vs Temperature

Figure 13. DEVSLP Pull Down Current vs Temperature

Figure 15. Output Ramp Time vs C_(dVdT)

Figure 17. Current Limit Accuracy vs Current Limit

Figure 19. Current Limit (% Normalized) vs R_(LIMIT) Resistor

Figure 21. Current Limit for R_(ILIM) = Open and Short vs Temperature

Figure 23. Fast Trip Threshold vs Current Limit

Figure 25. GAIN_(IMON) vs Temperature

Figure 27. R_ON vs Temperature Across Load Current

Figure 29. V_(REVTH) vs Temperature

Taken on 2-Layer board, 2oz.(0.08-mm thick) with GND plane area: 14 cm2 (Top) and 20 cm2 (bottom)

Figure 31. Thermal Shutdown Time vs Power Dissipation

V_(IN) = 11 V

Figure 33. Turn ON and OFF with Enable

R_(FLT)=100 kΩ

Figure 35. EN Turn OFF Delay : EN ↓ to Fault ↓

V_(IN) = 12 V	R_L = 12 Ω	R_(FLT)=100 kΩ

Figure 37. OVP Turn ON delay: OVP ↓ to Output Ramp ↑

V_(IN) = 12 V	R_L = 12 Ω	R_(FLT)= 100 kΩ
		R_(PGOOD)= 100 kΩ

Figure 39. Power Good Delay (Falling)

R_(FLT)=100 kΩ

R_(IMON)= 16.9 kΩ

Figure 41. Hot-Short: Fast Trip Response (Zoomed)

Figure 2. Input Supply Current vs Supply Voltage During Normal Operation

Figure 4. Input Supply Current vs Supply Voltage in DevSleep Mode

Figure 6. OVP Threshold Voltage vs Temperature

Figure 8. EN Threshold Voltage for Low IQ mode vs Temperature

Figure 10. Enable Turn OFF Delay vs Temperature

Figure 12. DEVSLP Threshold Voltage vs Temperature

Figure 14. GAIN_(dVdT) vs Temperature

Figure 16. Current Limit vs Current Limit Resistor

Figure 18. Current Limit vs Temperature Across R_(ILIM)

Thermal shutdown occurs when I_(LIM) = 5.3 A
and [V_(IN) - V_(OUT)] > 8 V

Figure 20. Current Limit Normalized (%) vs V_(IN) - V_(OUT)

Figure 22. Current Limit in DevSleep Mode vs Temperature

Figure 24. GAIN_(IMON)% Normalized vs Output Current

Figure 26. Current Monitor Output vs Output Current

Figure 28. OUT Leakage Current in Off State vs Temperature

Figure 30. V_(FWDTH) vs Temperature

V_(IN) = 4.5 V

Figure 32. Turn ON with Enable

R_(FLT)=100 kΩ

Figure 34. EN Turn ON Delay : EN ↑ to Output Ramp ↑

V_(IN) = 12 V

R_L = 12 Ω

R_(FLT)=100 kΩ

Figure 36. OVP Turn OFF delay: OVP ↑ to Fault ↓

V_(IN) = 12 V	R_L = 12 Ω	R_(FLT)= 100 kΩ
		R_(PGOOD)= 100 kΩ

Figure 38. Power Good Delay (Rising)

	R_(FLT) =100 kΩ	R_(IMON)= 16.9 kΩ

Figure 40. Hot-Short: Fast Trip Response and Current Regulation

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機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

7 Specifications

7.1 Absolute Maximum Ratings

7.2 Handling Ratings

7.3 Recommended Operating Conditions

7.4 Thermal Characteristics(1)

7.5 Electrical Characteristics

7.6 Timing Requirements

7.7 Typical Characteristics

7.4 Thermal Characteristics⁽¹⁾