9.3.1 Enable and Adjusting Undervoltage Lockout (UVLO)

The ENUV pin controls the ON/OFF state of the internal FET. A voltage V_(ENUV) < V_(ENF) on this pin turns off the internal FET, thus disconnecting IN from OUT.

Toggling the ENUV pin below V_{(ENF_RST)} resets the TPS25921L that has latched off due to a fault condition. The internal de-glitch delay on ENUV falling edge is kept low for quick detection of power failure. For applications where a higher de-glitch delay on ENUV is desired, or when the supply is particularly noisy, it is recommended to use an external filter capacitor from the ENUV terminal to GND.

The undervoltage lockout threshold can be programmed by using an external resistor divider from the supply IN terminal to the ENUV terminal to GND as shown in Figure 26. When an undervoltage or input power fail event is detected, the internal FET is quickly turned off, and FLT is asserted. If the undervoltage lockout function is not needed, the ENUV pin should be connected to the IN terminal. The ENUV terminal should not be left floating.

TPS25921 also implements internal undervoltage lockout (UVLO) circuitry on the IN pin. The device gets disabled when the IN terminal voltage falls below internal UVLO Threshold V_(UVF).

Figure 26. UVLO and OVP Thresholds Set By R₁, R₂ and R₃

9.3.2 Overvoltage Protection (OVP)

TPS25921 incorporates circuits to protect the system during overvoltage conditions. A resistor divider, connected from the supply to OVP terminal to GND (as shown in Figure 26), programs the overvoltage threshold. A voltage more than V_(OVPR) on the OVP pin turns off the internal FET and protects the downstream load. This pin should be tied to GND when not used.

9.3.3 Hot Plug-in and In-Rush Current Control

TPS25921 is designed to control the in-rush current upon insertion of a card into a live backplane or other "hot" power source. This limits the voltage sag on the backplane’s supply voltage and prevents unintended resets of the system power. A slew rate controlled startup (SS) also helps to eliminate conductive and radiated interference. An external capacitor from the SS pin to GND defines the slew rate of the output voltage at power-on (as shown in Figure 27). The equation governing slew rate at start-up is shown in Equation 1 :

Figure 27. Output Ramp Up Time t_dVdT is Set by C_(dVdT)

Equation 1.

Where:

• I_(SS) = 1 µA (typical)
• = Desired output slew rate
• GAIN_(SS) = ΔV_(OUT)/ΔV_(SS) gain = 4.85

The total ramp time (t_SS) of V_(OUT) for 0 to V_(IN) can be calculated using Equation 2:

Equation 2.

The inrush current, I_(INRUSH) can be calculated as

Equation 3.

The SS pin can be left floating to obtain a predetermined slew rate (t_SS) on the output. When terminal is left floating, the device sets an internal ramp rate of ~50V/ms for output (V_(OUT)) ramp.

Figure 36 and Figure 37 illustrate the inrush current control behavior of the device. For systems where load is present during start-up, the current never exceeds the overcurrent limit set by R_(ILIM) resistor for the application. For defining appropriate charging time/rate under different load conditions, refer to the Setting Output Voltage Ramp time (tSS) section.

9.3.4 Overload and Short Circuit Protection :

At all times load current is monitored by sensing voltage across an internal sense resistor. During overload events, current is limited to the current limit (I_LIMIT) programmed by R_(ILIM) resistor

Equation 4.

Equation 5.

• I_LIMIT is overload current limit in Ampere
• R_(ILIM) is the current limit programming resistor in kΩ

TPS25921 incorporates two distinct overcurrent protection levels: the current limit (I_LIMIT) and the fast-trip threshold (I_(FASTRIP)). The fast trip and current limit operations are shown in Figure 28.

Bias current on ILIM pin directly controls current-limiting behavior of the device, and PCB routing of this node must be kept away from any noisy (switching) signals.

9.3.4.2 Short Circuit Protection

During a transient short circuit event, the current through the device increases very rapidly. As current-limit amplifier cannot respond quickly to this event due to its limited bandwidth, the device incorporates a fast-trip comparator, with a threshold I_(FASTRIP). When the current through the internal FET exceeds I_(FASTRIP) (I_(OUT) > I_(FASTRIP)), this comparator shuts down the pass device within 3 µs and terminates the rapid short-circuit peak current. The I_(FASTRIP) threshold is dependent on programmed overload current limit and function of R_(ILIM). See Equation 6 for the calculation.

Equation 6.

where

• I_(FASTRIP) is fast trip current limit in Ampere
• R_(ILIM) is the current limit resistor in kΩ

9.3.4.4 Constant Current Limit Behavior during Overcurrent Faults

When power dissipation in the internal FET [P_D = (V_(IN) - V_(OUT)) × I_(OUT)] > 2 W, there is a ~1 to 20 % thermal fold back in the current limit value so that the regulated current drops from I_LIMIT to I_OS. Eventually, the device shuts down due to over temperature.

Figure 28. Overcurrent Protection Levels

9.3.5 FAULT Response

The FLT open-drain output is asserted (active low) during undervoltage, overvoltage and thermal shutdown conditions. The FLT signal remains asserted until the fault condition is removed and the device resumes normal operation. During thermal shutdown, TPS25921L version stays latched off, whereas TPS25921A commences an auto-retry cycle t_TSD(dly) millisecond after T_J < [T_(TSD) - 20°C]. For TPS25921L, thermal fault latch can be reset by cycling the ENUV pin below V_{(ENF_RST)} threshold. A nuisance fast trip does not trigger fault.

Connect FLT with a pull up resistor to Input or Output voltage rail. FLT may be left open or tied to ground when not used.

9.3.6 IN, OUT and GND Pins

The IN pin should be connected to the power source. A ceramic bypass capacitor close to the device from IN to GND is recommended to alleviate bus transients. The recommended operating voltage range is 4.5 V – 18 V.

The OUT pin should be connected to the load. V_(OUT) in the ON condition, is calculated using the Equation 7

Equation 7.

where, R_DS(ON) is the ON resistance of the internal FET.

GND terminal is the most negative voltage in the circuit and is used as a reference for all voltage reference unless otherwise specified.

9.3.7 Thermal Shutdown:

Internal over temperature shutdown disables/turns off the FET when T_J > 155°C (typical). The TPS25921L version latches off the internal FET, whereas TPS25921A commences an auto-retry cycle t_TSD(dly) milliseconds after T_J drops below [T_(TSD) - 20°C]. During the thermal shutdown, the fault pin FLT is pulled low to signal a fault condition.

9.4.1 Shutdown Control

The internal FET and hence the load current can be remotely switched off by taking the ENUV pin below its 1.34 V threshold with an open collector or open drain device as shown in Figure 29. Upon releasing the ENUV pin the device turns on with soft-start cycle.

Figure 29. Shutdown Control

9.4.2 Operational Overview of Device Functions

The Table 1 below elucidates the device functionality for various conditions