SLVS503F November 2003 – February 2020 TPS2490 , TPS2491
PRODUCTION DATA.
- 1 Features
- 2 Applications
- 3 Description
- 4 Revision History
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Detailed Description
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Mechanical, Packaging, and Orderable Information
7.3.7 PROG
The voltage applied to this pin (0.4 to 4 V) programs the power limit used by the constant power engine. Normally, a resistor divider R3/R4 is connected from VREF to PROG to set the power limit according to Equation 2:
where
- PLIM is the desired power limit of Q1
- ILIM is the current limit setpoint (see SENSE).
PLIM is determined by the desired thermal stress on Q1:
where
- TJ(MAX) is the maximum desired transient junction temperature of Q1
- TS(MAX) is the maximum case temperature prior to a start or restart.
VPROG is used in conjunction with VDS to compute the (scaled) current, ID_ALLOWED, by the constant power engine. ID_ALLOWED is compared by the gate amplifier to the actual ID, and used to generate a gate drive. If ID < ID_ALLOWED, the amplifier turns the gate of Q1 fully on because there is no overload condition; otherwise GATE is regulated to maintain the ID = ID_ALLOWED relationship.
A capacitor may be tied from PROG to ground to alter the natural constant power inrush current shape. If properly designed, the effect is to cause the leading step of current in Figure 13 to look like a ramp.
PROG is internally pulled to ground whenever EN, POR, or UVLO are not satisfied or the TPS2490 is latched off. This feature serves to discharge any capacitance connected to the pin. Do not apply voltages greater than 4 V to PROG. If the constant power limit is not used, PROG should be tied to VREF through a 47-kΩ resistor.