8.3.1 DETAILED PIN DESCRIPTIONS

8.3.1.9 PROG

A resistor from this pin to GND sets the maximum power permitted in the external MOSFET M₁ during inrush. Do not apply a voltage to this pin. If the constant power limit is not desired, use a PROG resistor of 4.99 kΩ. To set the maximum power, use Equation 1.

Equation 1.

To compute the Power limit based on an existing R_PROG use Equation 2.

Equation 2.

where P_LIM is the allowed power limit of MOSFET M₁. R_SENSE is the load-current-monitoring resistor connected between the VCC pin and the SENSE pin. R_PROG is the resistor connected from the PROG pin to GND. Both R_PROG and R_SENSE are in ohms and P_LIM is in watts. P_LIM is determined by the maximum allowed thermal stress of MOSFET M₁, given by Equation 3,

Equation 3.

where T_J(MAX) is the maximum desired transient junction temperature and T_C(MAX) is the maximum case temperature prior to a start or restart. R_?JC(MAX) is the junction-to-case thermal impedance of the pass MOSFET M₁ in units of °C/W. Both T_J(MAX) and T_C(MAX) are in °C.

8.3.1.10 SENSE

This pin connects to the negative terminal of R_SENSE. It provides a means of sensing the voltage across this resistor, as well as a way to monitor the drain-to-source voltage across the external FET. The current limit I_LIM is set by Equation 4.

Equation 4.

A fast trip shutdown occurs when V_{(VCC – VSENSE)} exceeds 60 mV.

8.3.1.11 TIMER

A capacitor C_T connected from the TIMER pin to GND determines the overload fault timing. TIMER sources 10 µA when an overload is present, and discharges C_T at 10 µA otherwise. M₁ is turned off when V_TIMER reaches 1.35 V. In an application implementing auto-retry after a fault, this capacitor also determines the period before the external MOSFET is re-enabled. A minimum timing capacitance of 1 nF is recommended to ensure proper operation of the fault timer. The value of C_T can be calculated from the desired fault time t_FLT, using Equation 5.

Equation 5.

The latch mode (TPS24710/12) or the retry mode (TPS24711/13) occurs if the load current exceeds the current limit threshold or the fast-trip shutdown threshold, While in latch mode, the TIMER pin continues to charge and discharge the attached capacitor periodically. In retry mode, the external MOSFET is disabled for sixteen cycles of TIMER charging and discharging. The TIMER pin is pulled to GND by a 2-mA current source at the end of the 16^th cycle of charging and discharging. The external MOSFET is then re-enabled. The TIMER pin capacitor, C_T, can also be discharged to GND during latch mode or retry mode by a 2-mA current source whenever any of the following occurs:

• V_EN is below its falling threshold.
• V_VCC drops below the UVLO threshold.

8.4.1 Board Plug In

Figure 27 and Figure 28 illustrate the inrush current that flows when a hot swap board under the control of the TPS24710/11/12/13 is plugged into a system bus. Only the bypass capacitor charge current and small bias currents are evident when a board is first plugged in. The TPS24710/11/12/13 is held inactive, for a short period while internal voltages stabilize. During this period GATE, PROG, TIMER are held low and PG, FLT, PGb, and FLTb are held open drain. When the voltage on the internal VCC rail exceeds approximately 1.5 V, the power-on reset (POR) circuit initializes the TPS24710/11/12/13 and a start-up cycle is ready to take place.

GATE, PROG, TIMER, PG, FLT, PGb, and FLTb are released after the internal voltages have stabilized and the external EN (enable) thresholds have been exceeded. The part begins sourcing current from the GATE pin to turn on MOSFET M₁. The TPS24710/11/12/13 monitors both the drain-to-source voltage across MOSFET M₁ and the drain current passing through it. Based on these measurements, the TPS24710/11/12/13 limits the drain current by controlling the gate voltage so that the power dissipation within the MOSFET does not exceed the power limit programmed by the user. The current increases as the voltage across the MOSFET decreases until finally the current reaches the current limit I_LIM.

Figure 27. Inrush Mode at Hot-Swap Circuit Insertion

8.4.2 Inrush Operation

After TPS24710/11/12/13 initialization is complete (as described in the Board Plug-In section) and EN is active, GATE is enabled (V_GATE starts increasing). When V_GATE reaches the MOSFET M1 gate threshold, a current flows into the downstream bulk storage capacitors. When this current exceeds the limit set by the power limit engine, the gate of the MOSFET is regulated by a feedback loop to make the MOSFET current rise in a controlled manner. This not only limits the inrush current charging capacitance but it also limits the power dissipation of the MOSFET to safe levels. A more complete explanation of the power limiting scheme is given in the section entitled Action of the Constant Power Engine. When Gate is enabled, the TIMER pin begins to charge the timing capacitor C_T with a current of approximately 10 μA. The TIMER pin continues to charge C_T until V_{(GATE – VCC)} reaches the timer activation voltage (5.9 V for V_VCC = 12 V). The TIMER then begins to discharge C_T with a current of approximately 10 μA. This indicates that the inrush mode is finished. If the TIMER exceeds its upper threshold of 1.35 V before V_{(GATE – VCC)} reaches the timer activation voltage, the GATE pin is pulled to GND and the hot-swap circuit enters either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13).

The power limit feature is disabled once the inrush operation is finished and the hotswap circuit becomes a circuit breaker. The TPS24710/11/12/13 will turn off the MOSFET, M1, after a fault timer period once the load exceeds the current limit threshold.

8.4.3 Action of the Constant-Power Engine

Figure 28 illustrates the operation of the constant-power engine during start-up. The circuit used to generate the waveforms of Figure 28 was programmed to a power limit of 29.3 W by means of the resistor connected between PROG and GND. At the moment current begins to flow through the MOSFET, a voltage of 12 V appears across it (input voltage V_VCC = 12 V), and the constant-power engine therefore allows a current of 2.44 A (equal to 29.3 W divided by 12 V) to flow. This current increases in inverse ratio as the drain-to-source voltage diminishes, so as to maintain a constant dissipation of 29.3 W. The constant-power engine adjusts the current by altering the reference signal fed to the current limit amplifier. The lower part of Figure 29 shows the measured power dissipated within the MOSFET, labeled FET PWR, remaining substantially constant during this period of operation, which ends when the current through the MOSFET reaches the current limit I_LIM. This behavior can be considered a form of foldback limiting, but unlike the standard linear form of foldback limiting, it allows the power device to operate near its maximum capability, thus reducing the start-up time and minimizing the size of the required MOSFET.

Figure 28. Computation of M₁ Power Stress During Start-Up

8.4.4 Circuit Breaker and Fast Trip

The TPS24710/11/12/13 monitors load current by sensing the voltage across R_SENSE. The TPS24710/11/12/13 incorporates two distinct thresholds: a current-limit threshold and a fast-trip threshold.

The functions of circuit breaker and fast-trip turn off are shown in Figure 29 through Figure 32.

Figure 29 shows the behavior of the TPS24710/11 when a fault in the output load causes the current passing through R_SENSE to increase to a value above the current limit but less than the fast-trip threshold. When the current exceeds the current-limit threshold, a current of approximately 10 μA begins to charge timing capacitor C_T. If the voltage on C_T reaches 1.35 V, then the external MOSFET is turned off. The TPS24710 latches off and the TPS24711 commences a restart cycle. In either event, fault pin FLTb pulls low to signal a fault condition. Overload between the current limit and the fast trip threshold is permitted for this period. This shutdown scheme is sometimes called an electronic circuit breaker.

The fast-trip threshold protects the system against a severe overload or a dead short circuit. When the voltage across the sense resistor R_SENSE exceeds the 60 mV fast-trip threshold, the GATE pin immediately pulls the external MOSFET gate to ground with approximately 1 A of current. This extremely rapid shutdown may generate disruptive transients in the system, in which case a low-value resistor inserted between the GATE pin and the MOSFET gate can be used to moderate the turn off current. The fast-trip circuit holds the MOSFET off for only a few microseconds, after which the TPS24710/11/12/13 turns back on slowly, allowing the current-limit feedback loop to take over the gate control of M₁. Then the hot-swap circuit goes into either latch mode (TPS24710/12) or auto-retry mode (TPS24711/13). Figure 31 and Figure 32 illustrate the behavior of the system implementing TPS24710/11 when the current exceeds the fast-trip threshold.

Figure 29. Circuit Breaker Mode During Over Load Condition

Figure 30. Partial Diagram of the TPS24710/11/12/13 With Selected External Components

Figure 31. Current Limit During Output Load Short Circuit Condition (Overview)

Figure 32. Current Limit During Output-Load Short-Circuit Condition (Onset)

8.4.5 Automatic Restart

The TPS24711/13 automatically initiates a restart after a fault has caused it to turn off the external MOSFET M₁. Internal control circuits use C_T to count 16 cycles before re-enabling M₁ as shown in Figure 33 (TPS24711). This sequence repeats if the fault persists. The timer has a 1 : 1 charge-to-discharge current ratio. For the very first cycle, the TIMER pin starts from 0 V and rises to the upper threshold of 1.35 V and subsequently falls to 0.35 V before restarting. For the following 16 cycles, 0.35 V is used as the lower threshold. This small duty cycle often reduces the average short-circuit power dissipation to levels associated with normal operation and eliminates special thermal considerations for surviving a prolonged output short.

Figure 33. Auto-Restart Cycle Timing

Figure 34. Latch After Overload Fault

8.4.6 PG, FLT, PGb, FLTb, and Timer Operations

The open-drain PG/PGb (PG is for TPS24712/13 and PGb is for TPS24710/11) output provides a deglitched end-of-inrush indication based on the voltage across M₁. PG/PGb is useful for preventing a downstream dc/dc converter from starting while its input capacitor C_OUT is still charging. PG goes active-high and PGb goes active-low about 3.4 ms after C_OUT is charged. This delay allows M₁ to fully turn on and any transients in the power circuits to end before the converter starts up. This type of sequencing prevents the downstream converter from demanding full current before the power-limiting engine allows the MOSFET to conduct the full current set by the current limit I_LIM. Failure to observe this precaution may prevent the system from starting. The pullup resistor shown on the PG/PGb pin in the typical application diagram on the front page is illustrative only; the actual connection to the converter depends on the application. The PG/PGb pin may indicate that inrush has ended before the MOSFET is fully enhanced, but the downstream capacitor will have been charged to substantially its full operating voltage. Care should be taken to ensure that the MOSFET on-resistance is sufficiently small to ensure that the voltage drop across this transistor is less than the minimum power-good threshold of 140 mV. After the hot-swap circuit successfully starts up, the PG pin can return to a low-impedance status and PGb to high-impedance status whenever the drain-to-source voltage of MOSFET M₁ exceeds its upper threshold of 340 mV, which presents the downstream converters a warning flag. This flag may occur as a result of overload fault, output short fault, input overvoltage, higher die temperature, or the GATE shutdown by UVLO and EN.

FLT/FLTb (FLT is for TPS24712/13 and FLTb is for TPS24710/11) is an indicator that the allowed fault-timer period during which the load current can exceed the programmed current limit (but not the fast-trip threshold) has expired. The fault timer starts when a current of approximately 10 μA begins to flow into the external capacitor, C_T, and ends when the voltage of C_T reaches TIMER upper threshold, i.e., 1.35 V. FLT goes high and FLTb pulls low at the end of the fault timer. Otherwise, FLT assumes a low-impedance state and FLTb a high-impedance state.

The fault-timer state requires an external capacitor C_T connected between the TIMER pin and GND pin. The length of the fault timer is the charging time of C_T from 0 V to its upper threshold of 1.35 V. The fault timer begins to count under any of the following three conditions:

1. In the inrush mode, TIMER begins to source current to the timer capacitor, C_T, when MOSFET M₁ is enabled. TIMER begins to sink current from the timer capacitor, C_T when V_{(GATE – VCC)} exceeds the timer activation voltage (see the Inrush Operation section). If V_{(GATE – VCC)} does not reach the timer activation voltage before TIMER reaches 1.35 V, then the TPS24710/11/12/13 disables the external MOSFET M₁. After the MOSFET turns off, the timer goes into either latch mode (TPS24710/12) or retry mode (TPS24711/13).
2. In an overload fault, TIMER begins to source current to the timer capacitor, C_T, when the load current exceeds the programmed current limits. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).
3. In output short-circuit fault, TIMER begins to source current to the timer capacitor, C_T, when the load current exceeds the programmed current limits following a fast-trip shutdown of M₁. When the timer capacitor voltage reaches its upper threshold of 1.35 V, TIMER begins to sink current from the timer capacitor, C_T, and the GATE pin is pulled to ground. After the fault timer period, TIMER may go into latch mode (TPS24710/12) or retry mode (TPS24711/13).

If the fault current drops below the programmed current limit within the fault timer period, V_TIMER decreases and the pass MOSFET remains enabled.

The behaviors of TIMER are different in the latch mode (TPS24710/12) and retry mode (TPS24711/13). If the timer capacitor reaches the upper threshold of 1.35 V, then:

• In latch mode, the GATE remains low and the TIMER pin continues to charge and discharge the attached capacitor periodically until TPS24710/12 is disabled by UVLO or EN as shown in Figure 34.
• In retry mode, TIMER charges and discharges C_T between the lower threshold of 0.35 V and the upper threshold of 1.35 V for sixteen cycles before the TPS24711/13 attempts to re-start. The TIMER pin is pulled to GND at the end of the 16^th cycle of charging and discharging and then ramps from 0 V to 1.35 V for the initial half-cycle in which the GATE pin sources current. This periodic pattern is stopped once the overload fault is removed or the TPS24711/13 is disabled by UVLO or EN.

8.4.7 Overtemperature Shutdown

The TPS24710/11/12/13 includes a built-in overtemperature shutdown circuit designed to disable the gate driver if the die temperature exceeds approximately 140°C. An overtemperature condition also causes the FLT, PG, FLTb and PGb pins to go to high-impedance states. Normal operation resumes once the die temperature has fallen approximately 10°C.

8.4.8 Start-Up of Hot-Swap Circuit by VCC or EN

The connection and disconnection between a load and the system bus are controlled by turning on and turning off the MOSFET, M₁.

The TPS24710/11/12/13 has two ways to turn on MOSFET M₁:

1. Increasing V_VCC above UVLO upper threshold while EN is already higher than its upper threshold sources current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M₁.
2. Increasing EN above its upper threshold while V_VCC is already higher than UVLO upper threshold sources current to the GATE pin. After an inrush period, TPS24710/11/12/13 fully turns on MOSFET M₁.

The EN pin can be used to start up the TPS24710/11/12/13 at a selected input voltage V_VCC.

To isolate the load from the system bus, the GATE pin sinks current and pulls the gate of MOSFET M₁ low. The MOSFET can be disabled by any of the following conditions: UVLO, EN, load current above current limit threshold, hard short at load, or OTSD. Three separate conditions pull down the GATE pin:

1. GATE is pulled down by an 11-mA current source when any of the following occurs.
   • The fault timer expires during an overload current fault (V_SENSE > 25 mV).
   • V_EN is below its falling threshold.
   • V_VCC drops below the UVLO threshold.
2. GATE is pulled down by a 1-A current source for 13.5 µs when a hard output short circuit occurs and V_{(VCC – SENSE)} is greater than 60 mV, i.e., the fast-trip shutdown threshold. After fast-trip shutdown is complete, an 11-mA sustaining current ensures that the external MOSFET remains off.
3. GATE is discharged by a 20-kΩ resistor to GND if the chip die temperature exceeds the OTSD rising threshold.