ZHCSCT9D August 2014 – October 2016 TCA9538
PRODUCTION DATA.
- 1 特性
- 2 應用范圍
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
- 6 Specifications
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機械、封裝和可訂購信息
10 Power Supply Recommendations
10.1 Power-On Reset Requirements
In the event of a glitch or data corruption, the TCA9538 can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.
The two types of power-on reset are shown in and Figure 29.
Figure 29. VCC is Lowered Below the POR Threshold, Then Ramped Back Up to VCC
Table 8 specifies the performance of the power-on reset feature for the TCA9538 for both types of power-on reset.
Table 8. Recommended Supply Sequencing And Ramp Rates(1)
| PARAMETER | MIN | MAX | UNIT | ||
|---|---|---|---|---|---|
| VCC_FT | Fall rate | See Figure 29 | 1 | ms | |
| VCC_RT | Rise rate | See Figure 29 | 0.1 | ms | |
| VCC_TRR | Time to re-ramp (when VCC drops to VPOR_MIN – 50 mV or when VCC drops to GND) | See Figure 29 | 2 | μs | |
| VCC_GH | Level that VCC can glitch down to, but not cause a functional disruption when VCC_GW = 1 µs | See Figure 30 | 1.2 | V | |
| VCC_GW | Glitch width that does not cause a functional disruption when VCC_GH = 0.5 × VCC (For VCC > 3 V) | See Figure 30 | 10 | μs | |
Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (VCC_GW) and height (VCC_GH) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 30 and Table 8 provide more information on how to measure these specifications.
Figure 30. Glitch Width and Glitch Height
VPOR is critical to the power-on reset. VPOR is the voltage level at which the reset condition is released and all the registers and the I2C/SMBus state machine are initialized to their default states. The value of VPOR differs based on the VCC being lowered to or from 0. Figure 31 and Table 8 provide more details on this specification.
Figure 31. VPOR