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SCPS222C May 2010 – October 2015 TCA8418E

PRODUCTION DATA.

封裝選項

機械數據 (封裝 | 引腳)

YFP|25
- MXBG084M

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

10 Power Supply Recommendations

In the event of a glitch or data corruption, TCA8418E can be reset to its default conditions by using the power-on reset feature. Power-on reset requires that the device go through a power cycle to be completely reset. This reset also happens when the device is powered on for the first time in an application.

The two types of power-on reset are shown in Figure 36 and Figure 37.

Figure 36. V_CC is Lowered Below 0.2 V or 0 V and Then Ramped Up to V_CC

Figure 37. V_CC is Lowered Below the POR Threshold, Then Ramped Back Up to V_CC

Table 28 specifies the performance of the power-on reset feature for TCA8418E for both types of power-on reset.

Table 28. Recommended Supply Sequencing and Ramp Rates⁽¹⁾

PARAMETER			MIN	MAX	UNIT
V_{CC_FT}	Fall rate	See Figure 36	1	100	ms
V_{CC_RT}	Rise rate	See Figure 36	0.01	100	ms
V_{CC_TRR_GND}	Time to re-ramp (when V_CC drops to GND)	See Figure 36	0.001		ms
V_{CC_TRR_POR50}	Time to re-ramp (when V_CC drops to V_{POR_MIN} – 50 mV)	See Figure 37	0.001		ms
V_{CC_GH}	Level that V_CCP can glitch down to, but not cause a functional disruption when V_{CCX_GW} = 1 μs	See Figure 38		1.2	V
V_{CC_GW}	Glitch width that will not cause a functional disruption when V_{CCX_GH} = 0.5 × V_CCx	See Figure 38		10	μs
V_PORF	Voltage trip point of POR on falling V_CC		0.76	1.15	V
V_PORR	Voltage trip point of POR on rising V_CC		1.03	1.43	V

(1) T_A = –40°C to 85°C (unless otherwise noted)

Glitches in the power supply can also affect the power-on reset performance of this device. The glitch width (V_{CC_GW}) and height (V_{CC_GH}) are dependent on each other. The bypass capacitance, source impedance, and device impedance are factors that affect power-on reset performance. Figure 38 and Table 28 provide more information on how to measure these specifications.

Figure 38. Glitch Width and Glitch Height

V_POR is critical to the power-on reset. V_POR is the voltage level at which the reset condition is released and all the registers and the I²C/SMBus state machine are initialized to their default states. The value of V_POR differs based on the V_CC being lowered to or from 0. Figure 39 and Table 28 provide more details on this specification.

Figure 39. V_POR

For proper operation of the power-on reset feature, use as directed in the previous figures and table above.