ZHCSJB4D April 2019 – January 2024 TAS2563
PRODUCTION DATA
- 1
- 1 特性
- 2 應(yīng)用
- 3 說(shuō)明
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Thermal Information
- 5.5 Electrical Characteristics
- 5.6 I2C Timing Requirements
- 5.7 SPI Timing Requirements
- 5.8 PDM Port Timing Requirements
- 5.9 TDM Port Timing Requirements
- 5.10 Timing Diagrams
- 5.11 Typical Characteristics
- 6 Parameter Measurement Information
-
7 Detailed Description
- 7.1 Overview
- 7.2 Functional Block Diagram
- 7.3
Feature Description
- 7.3.1 PurePath Console 3 Software
- 7.3.2 Device Mode and Address Selection
- 7.3.3 General I2C Operation
- 7.3.4 General SPI Operation
- 7.3.5 Single-Byte and Multiple-Byte Transfers
- 7.3.6 Single-Byte Write
- 7.3.7 Multiple-Byte Write and Incremental Multiple-Byte Write
- 7.3.8 Single-Byte Read
- 7.3.9 Multiple-Byte Read
- 7.3.10 Register Organization
- 7.3.11 Operational Modes
- 7.3.12 Faults and Status
- 7.3.13 Digital Input Pull Downs
- 7.4 Device Functional Modes
- 7.5
Register Maps
- 7.5.1 Register Summary Table Page=0x00
- 7.5.2 PAGE (page=0x00 address=0x00) [reset=0h]
- 7.5.3 SW_RESET (page=0x00 address=0x01) [reset=0h]
- 7.5.4 PWR_CTL (page=0x00 address=0x02) [reset=Eh]
- 7.5.5 PB_CFG1 (page=0x00 address=0x03) [reset=20h]
- 7.5.6 MISC_CFG1 (page=0x00 address=0x04) [reset=C6h]
- 7.5.7 MISC_CFG2 (page=0x00 address=0x05) [reset=22h]
- 7.5.8 TDM_CFG0 (page=0x00 address=0x06) [reset=9h]
- 7.5.9 TDM_CFG1 (page=0x00 address=0x07) [reset=2h]
- 7.5.10 TDM_CFG2 (page=0x00 address=0x08) [reset=4Ah]
- 7.5.11 TDM_CFG3 (page=0x00 address=0x09) [reset=10h]
- 7.5.12 TDM_CFG4 (page=0x00 address=0x0A) [reset=13h]
- 7.5.13 TDM_CFG5 (page=0x00 address=0x0B) [reset=2h]
- 7.5.14 TDM_CFG6 (page=0x00 address=0x0C) [reset=0h]
- 7.5.15 TDM_CFG7 (page=0x00 address=0x0D) [reset=4h]
- 7.5.16 TDM_CFG8 (page=0x00 address=0x0E) [reset=5h]
- 7.5.17 TDM_CFG9 (page=0x00 address=0x0F) [reset=6h]
- 7.5.18 TDM_CFG10 (page=0x00 address=0x10) [reset=7h]
- 7.5.19 DSP Mode & TDM_DET (page=0x00 address=0x11) [reset=7Fh]
- 7.5.20 LIM_CFG0 (page=0x00 address=0x12) [reset=12h]
- 7.5.21 LIM_CFG1 (page=0x00 address=0x13) [reset=76h]
- 7.5.22 DSP FREQUENCY & BOP_CFG0 (page=0x00 address=0x14) [reset=1h]
- 7.5.23 BOP_CFG0 (page=0x00 address=0x15) [reset=2Eh]
- 7.5.24 BIL_and_ICLA_CFG0 (page=0x00 address=0x16) [reset=60h]
- 7.5.25 BIL_ICLA_CFG1 (page=0x00 address=0x17) [reset=0h]
- 7.5.26 GAIN_ICLA_CFG0 (page=0x00 address=0x18) [reset=0h]
- 7.5.27 ICLA_CFG1 (page=0x00 address=0x19) [reset=0h]
- 7.5.28 INT_MASK0 (page=0x00 address=0x1A) [reset=FCh]
- 7.5.29 INT_MASK1 (page=0x00 address=0x1B) [reset=A6h]
- 7.5.30 INT_MASK2 (page=0x00 address=0x1C) [reset=DFh]
- 7.5.31 INT_MASK3 (page=0x00 address=0x1D) [reset=FFh]
- 7.5.32 INT_LIVE0 (page=0x00 address=0x1F) [reset=0h]
- 7.5.33 INT_LIVE1 (page=0x00 address=0x20) [reset=0h]
- 7.5.34 INT_LIVE3 (page=0x00 address=0x21) [reset=0h]
- 7.5.35 INT_LIVE4 (page=0x00 address=0x22) [reset=0h]
- 7.5.36 INT_LTCH0 (page=0x00 address=0x24) [reset=0h]
- 7.5.37 INT_LTCH1 (page=0x00 address=0x25) [reset=0h]
- 7.5.38 INT_LTCH3 (page=0x00 address=0x26) [reset=0h]
- 7.5.39 INT_LTCH4 (page=0x00 address=0x27) [reset=0h]
- 7.5.40 VBAT_MSB (page=0x00 address=0x2A) [reset=0h]
- 7.5.41 VBAT_LSB (page=0x00 address=0x2B) [reset=0h]
- 7.5.42 TEMP (page=0x00 address=0x2C) [reset=0h]
- 7.5.43 INT & CLK CFG (page=0x00 address=0x30) [reset=19h]
- 7.5.44 DIN_PD (page=0x00 address=0x31) [reset=40h]
- 7.5.45 MISC (page=0x00 address=0x32) [reset=80h]
- 7.5.46 BOOST_CFG1 (page=0x00 address=0x33) [reset=34h]
- 7.5.47 BOOST_CFG2 (page=0x00 address=0x34) [reset=4Bh]
- 7.5.48 BOOST_CFG3 (page=0x00 address=0x35) [reset=74h]
- 7.5.49 MISC (page=0x00 address=0x3B) [reset=58h]
- 7.5.50 TG_CFG0 (page=0x00 address=0x3F) [reset=0h]
- 7.5.51 BST_ILIM_CFG0 (page=0x00 address=0x40) [reset=36h]
- 7.5.52 PDM_CONFIG0 (page=0x00 address=0x41) [reset=1h]
- 7.5.53 DIN_PD & PDM_CONFIG3 (page=0x00 address=0x42) [reset=F8h]
- 7.5.54 ASI2_CONFIG0 (page=0x00 address=0x43) [reset=8h]
- 7.5.55 ASI2_CONFIG1 (page=0x00 address=0x44) [reset=0h]
- 7.5.56 ASI2_CONFIG2 (page=0x00 address=0x45) [reset=1h]
- 7.5.57 ASI2_CONFIG3 (page=0x00 address=0x46) [reset=FCh]
- 7.5.58 PVDD_MSB_DSP (page=0x00 address=0x49) [reset=0h]
- 7.5.59 PVDD_LSB_DSP (page=0x00 address=0x4A) [reset=0h]
- 7.5.60 REV_ID (page=0x00 address=0x7D) [reset=0h]
- 7.5.61 I2C_CKSUM (page=0x00 address=0x7E) [reset=0h]
- 7.5.62 BOOK (page=0x00 address=0x7F) [reset=0h]
- 8 Application and Implementation
- 9 Power Supply Recommendations
- 10Layout
- 11Device and Documentation Support
- 12Revision History
- 13Mechanical, Packaging, and Orderable Information
封裝選項(xiàng)
請(qǐng)參考 PDF 數(shù)據(jù)表獲取器件具體的封裝圖。
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- YBG|42
- RPP|32
散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)
訂購(gòu)信息
3 說(shuō)明
TAS2563 是一款經(jīng)過(guò)優(yōu)化、可將高峰值功率高效地驅(qū)動(dòng)到小型揚(yáng)聲器的數(shù)字輸入 D 級(jí)音頻放大器。該 D 類(lèi)放大器能夠在 3.6V 的電池電壓下使用集成式 11.5V H 類(lèi)升壓功能將 6.1W 峰值功率提供給 4Ω 負(fù)載，或在升壓旁路模式下使用外部 12V 電源將 10W 峰值功率提供給 4Ω 負(fù)載。
片上低延遲 DSP 支持德州儀器 (TI) 的 SmartAmp 揚(yáng)聲器保護(hù)算法。集成的電流和電壓檢測(cè)功能可對(duì)揚(yáng)聲器進(jìn)行實(shí)時(shí)監(jiān)測(cè)，從而在改變峰值聲壓級(jí) (SPL) 的同時(shí)保持揚(yáng)聲器不受損壞。
集成的超前 H 級(jí)升壓功能可在播放期間動(dòng)態(tài)調(diào)整升壓電壓，從而提高電池供電型系統(tǒng)的效率并延長(zhǎng)電池壽命。對(duì)于穩(wěn)壓壁式供電型系統(tǒng)，TAS2563 還具有升壓旁路模式，支持高達(dá) 16V 的電源電壓以實(shí)現(xiàn)更高的輸出功率。
兩個(gè) PDM 麥克風(fēng)輸入簡(jiǎn)化了雙向音頻系統(tǒng)的音頻信號(hào)鏈，能夠?qū)?shù)字麥克風(fēng)與主機(jī)處理器連接起來(lái)。電池跟蹤峰值電壓限制器具有欠壓保護(hù)功能，可以優(yōu)化放大器在整個(gè)充電周期中的余量，從而防止系統(tǒng)關(guān)斷。
器件信息(1)
| 器件型號(hào) | 封裝 | 封裝尺寸（標(biāo)稱(chēng)值） |
|---|---|---|
| TAS2563 | DSBGA | 2.5mm × 3mm |
| TAS2563 | QFN | 4.5mm x 4mm |
(1) 如需了解所有可用封裝，請(qǐng)參閱數(shù)據(jù)表末尾的可訂購(gòu)產(chǎn)品附錄。
簡(jiǎn)化版原理圖