ZHCSOE9 April 2022 SN74LXCH1T45
PRODUCTION DATA
- 1 特性
- 2 應用
- 3 說明
- 4 Revision History
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics
- 6.6 Switching Characteristics, VCCA = 1.2 ± 0.1 V
- 6.7 Switching Characteristics, VCCA = 1.5 ± 0.1 V
- 6.8 Switching Characteristics, VCCA = 1.8 ± 0.15 V
- 6.9 Switching Characteristics, VCCA = 2.5 ± 0.2 V
- 6.10 Switching Characteristics, VCCA = 3.3 ± 0.3 V
- 6.11 Switching Characteristics, VCCA = 5.0 ± 0.5 V
- 6.12 Switching Characteristics: Tsk, TMAX
- 6.13 Operating Characteristics
- 6.14 Typical Characteristics
- 7 Parameter Measurement Information
-
8 Detailed Description
- 8.1 Overview
- 8.2 Functional Block Diagram
- 8.3
Feature Description
- 8.3.1 CMOS Schmitt-Trigger Inputs
- 8.3.2 Balanced High-Drive CMOS Push-Pull Outputs
- 8.3.3 Partial Power Down (Ioff)
- 8.3.4 VCC Isolation and VCC Disconnect
- 8.3.5 Over-Voltage Tolerant Inputs
- 8.3.6 Glitch-Free Power Supply Sequencing
- 8.3.7 Negative Clamping Diodes
- 8.3.8 Fully Configurable Dual-Rail Design
- 8.3.9 Supports High-Speed Translation
- 8.3.10 Bus-Hold Data Inputs
- 8.4 Device Functional Modes
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12Device and Documentation Support
- 13Mechanical, Packaging, and Orderable Information
封裝選項
機械數據 (封裝 | 引腳)
散熱焊盤機械數據 (封裝 | 引腳)
- DRY|6
訂購信息
8.3.10 Bus-Hold Data Inputs
Each data input on this device includes a weak latch that maintains a valid logic level on the input. The state of these latches is unknown at startup and remains unknown until the input has been forced to a valid high or low state. After data is sent through a channel, the latch maintains the previous state on the input (if the line is left floating). It is not recommended to use pull-up or pull-down resistors together with a bus-hold input, as it may cause undefined inputs to occur which leads to excessive current consumption.
Bus-hold data inputs prevent floating inputs on this device. The Implications of Slow or Floating CMOS Inputs application report explains the problems associated with leaving the CMOS inputs floating. These latches remain active at all times, independent of all control signals such as direction control or output enable. The latches also remain active when the device is in the partial power down state, corresponding supply is still present, or when the I/O's are floated. The Bus-Hold Circuit application report has additional details regarding bus-hold inputs.
Figure 8-3 Schematic Description of Location of
Bus-Hold Circuits