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ZHCSFI0 September 2016 SN65HVS883

PRODUCTION DATA.

封裝選項

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

			MIN	MAX	UNIT
V24	Field power input	V24	–0.3	36	V
V_IPx	Field digital inputs	IPx	–0.3	36	V
V_ID	Voltage at any logic input	DB0, DB1, CLK, SIP, CE, LD	–0.5	6	V
I_O	Output current	CHOK, SOP		±8	mA
P_TOT	Continuous total power dissipation		See Thermal Information table
T_J	Junction temperature			170	°C

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All pins	±4000	V
		Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	IPx,V24	±15000
		Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	All pins	±1000
		Machine Mode⁽³⁾	All pins	±100

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

(3) JEDEC Standard 22, Method A115-A.

6.3 Recommended Operating Conditions

		MIN	TYP	MAX	UNIT
V₂₄	Field supply voltage	10	24	34	V
V_IPL	Field input low-state input voltage⁽¹⁾	0		4	V
V_IPH	Field input high-state input voltage⁽¹⁾	10		34	V
V_IL	Logic low-state input voltage	0		0.8	V
V_IH	Logic high-state input voltage	2		5.5	V
R_LIM	Current limiter resistor	17	25	500	kΩ
f_IP	Input data rate⁽²⁾	0		1	Mbps
T_J				150	°C
T_A		–40		85	°C

(1) Field input voltages correspond to an input resistor of R_IN = 1.2 kΩ

(2) Maximum data rate corresponds to 0 ms debounce time, (DB0 = open, DB1 = FGND), and R_IN = 0 Ω

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			SN65HVS883	UNIT
			PWP (HTSSOP)
			28 PINS
R_θJA	Junction-to-ambient thermal resistance		35	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance		4.27	°C/W
R_θJB	Junction-to-board thermal resistance		15	°C/W
PD	Device power dissipation	I_LOAD = 50 mA, R_IN = 0, IPO–IP7 = V24 = 30 V, RE7 = FGND, f_CLK = 100 MHz, I_IP-LIM and I_CC = worst case with R_LIM = 25 kΩ	2591	mW

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

all voltages measured against FGND unless otherwise stated, see Figure 12

SYMBOL	PARAMETER	PIN	TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_TH–(IP)	Low-level device input threshold voltage	_IP0–IP7	18 V< V24 < 34 V, R_IN = 0 Ω , R_LIM = 25 kΩ	4	4.3		V
V_TH+(IP)	High-level device input threshold voltage				5.2	5.5	V
V_HYS(IP)	Device input hysteresis				0.9		V
V_TH–(IN)	Low-level field input threshold voltage	measured at field side of R_IN	18 V < V24 < 34 V, R_IN = 1.2 kΩ ± 5%, R_LIM = 25 kΩ	6	8.4		V
V_TH+(IN)	High-level field input threshold voltage				9.4	10	V
V_HYS(IN)	Field input hysteresis				1		V
V_TH–(V24)	Low-level V24-monitor threshold voltage	V24		15	16.05		V
V_TH+(V24)	High-level V24-monitor threshold voltage				16.8	18	V
V_HYS(V24)	V24-monitor hysteresis				0.75		V
R_IP	Input resistance	IP0–IP7	3 V < V_IPx < 6 V, R_IN = 1.2 kΩ ± 5%, R_LIM = 25 kΩ	1.4	1.83	2.3	kΩ
I_IP-LIM	Input current limit	IP0–IP7	10 V < V_IPx < 34 V, R_LIM = 25 kΩ	3.15	3.6	4	mA
V_OL	Logic low-level output voltage	SOP, CHOK	I_OL = 20 μA			0.4	V
V_OH	Logic high-level output voltage	SOP, CHOK	I_OH = –20 μA	4			V
I_IL	Logic input leakage current	DB0, DB1, SIP, LD, CE, CLK		–50		50	μA
I_RE-on	RE on-state current	RE0–RE7	R_LIM = 25 kΩ, RE_X = FGND	2.8	3.15	3.5	mA
I_CC(V24)	Supply current	V24	IP0 to IP7 = V24, 5VOP = open, RE_X = FGND, All logic inputs open			8.7	mA
V_O(5V)	Linear regulator output voltage	5VOP	18 V < V24 < 34 V, no load	4.5	5	5.5	V
V_O(5V)	Linear regulator output voltage		18 V < V24 < 34 V, I_L = 50 mA	4.5	5	5.5	V
I_LIM(5V)	Linear regulator output current limit				115		mA
ΔV₅/ΔV₂₄	Line regulation	5VOP, V24	18 V < V24 < 34 V, I_L = 5 mA			2	mV/V
t_DB	Debounce times of input channels	IP0–IP7	DB0 = open, DB1 = FGND		0		ms
			DB0 = FGND, DB1 = open		1
			DB0 = DB1 = open		3
t_DB-HL	Voltage monitor debounce time after V24 < 15 V (CHOK turns low)	V24, CHOK			1		ms
t_DB-LH	Voltage monitor debounce time after V24 > 18 V (CHOK turns high)	V24, CHOK			6		ms
T_SHDN	Shutdown temperature				170		°C

6.6 Timing Requirements

over operating free-air temperature range (unless otherwise noted)

SYMBOL	PARAMETER		MIN	MAX	UNIT
t_W1	CLK pulse width	See Figure 9	4		ns
t_W2	LD pulse width	See Figure 7	6		ns
t_SU1	SIP to CLK setup time	See Figure 10	4		ns
t_H1	SIP to CLK hold time	See Figure 10	2		ns
t_SU2	Falling edge to rising edge (CE to CLK) setup time	See Figure 11	4		ns
t_REC	LD to CLK recovery time	See Figure 8	2		ns
f_CLK	Clock pulse frequency (50% duty cycle)	See Figure 9	DC	100	MHz

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

SYMBOL	PARAMETER	TEST CONDITIONS	MAX	UNIT
t_PLH1, t_PHL1	CLK to SOP	C_L = 15 pF, see Figure 9	10	ns
t_PLH2, t_PHL2	LD to SOP	C_L = 15 pF, see Figure 7	14	ns
t_r, t_f	Rise and fall times	C_L = 15 pF, see Figure 9	5	ns

6.8 Typical Input Characteristics

	R_IN = 1.2 kΩ	a) I_IP-LIM= 2.5 mA (R_LIM = 36.1 kΩ)
		b) I_IP-LIM= 3.0 mA (R_LIM = 30.1 kΩ)
		c) I_IP-LIM= 3.6 mA (R_LIM = 24.9 kΩ)

Figure 1. Typical Input Characteristics

V24 = 24 V	V_IN = 24 V	R_IN = 1.2 kΩ
R_LIM = 24.9 kΩ

Figure 2. Typical Current Limiter Variation vs Ambient Temperature

V24 = 24 V	R_IN = 1.2 kΩ	R_LIM = 24.9 kΩ

Figure 3. Typical Limiter Threshold Voltage Variation vs Ambient Temperature

6.9 Typical Voltage Regulator Performance Characteristics

I_LOAD = 5 mA	T_A = 27°C

Figure 4. Line Regulation

R_LOAD = 100 Ω

Figure 6. Output Voltage vs Input Voltage

I_LOAD = 0 mA

Figure 5. Output Voltage vs Ambient Temperature

封裝選項

機械數據 (封裝 | 引腳)

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Timing Requirements

6.7 Switching Characteristics

6.8 Typical Input Characteristics

6.9 Typical Voltage Regulator Performance Characteristics