ZHCSCB3D March 2014 – March 2018 PCM1860 , PCM1861 , PCM1862 , PCM1863 , PCM1864 , PCM1865
PRODUCTION DATA.
CLK_DIV_PLL_SCK is the alternate name for this register.
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| RSV | DIVNUM | ||||||
| R/W-0b | R/W-000 0111b | ||||||
| Bit | Field | Type | Reset | Description |
|---|---|---|---|---|
| 7 | RSV | R/W | 0 | Reserved. Do not access. |
| 6-0 | DIV_NUM | R/W | 000 0111b | Set PLL SCK Clock Output Divider for SCK Out (when enabled)
Used in BCK slave mode or master mode where PLL-ed SCK Out is required. Requires MST_SCK_SRC (0x20) to be enabled. Divider value: 0: 1 1: 1/2 2: 1/3 3: 1/4 : 7: 1/8 (default) : 127: 1/128 |