ZHCSIR8F August 2009 – September 2018 MSP430F5418 , MSP430F5419 , MSP430F5435 , MSP430F5436 , MSP430F5437 , MSP430F5438
PRODUCTION DATA.
- 1器件概述
- 2修訂歷史記錄
- 3Device Comparison
- 4Terminal Configuration and Functions
-
5Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Recommended Operating Conditions
- 5.4 Active Mode Supply Current Into VCC Excluding External Current
- 5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current
- 5.6 Thermal Resistance Characteristics
- 5.7 Schmitt-Trigger Inputs – General-Purpose I/O
- 5.8 Inputs – Ports P1 and P2
- 5.9 Leakage Current – General-Purpose I/O
- 5.10 Outputs – General-Purpose I/O (Full Drive Strength)
- 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
- 5.12 Output Frequency – General-Purpose I/O
- 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
- 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
- 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
- 5.16 Crystal Oscillator, XT1, High-Frequency Mode
- 5.17 Crystal Oscillator, XT2
- 5.18 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
- 5.19 Internal Reference, Low-Frequency Oscillator (REFO)
- 5.20 DCO Frequency
- 5.21 PMM, Brownout Reset (BOR)
- 5.22 PMM, Core Voltage
- 5.23 PMM, SVS High Side
- 5.24 PMM, SVM High Side
- 5.25 PMM, SVS Low Side
- 5.26 PMM, SVM Low Side
- 5.27 Wake-up Times From Low-Power Modes
- 5.28 Timer_A
- 5.29 Timer_B
- 5.30 USCI (UART Mode) Clock Frequency
- 5.31 USCI (UART Mode)
- 5.32 USCI (SPI Master Mode) Clock Frequency
- 5.33 USCI (SPI Master Mode)
- 5.34 USCI (SPI Slave Mode)
- 5.35 USCI (I2C Mode)
- 5.36 12-Bit ADC, Power Supply and Input Range Conditions
- 5.37 12-Bit ADC, External Reference
- 5.38 12-Bit ADC, Built-In Reference
- 5.39 12-Bit ADC, Timing Parameters
- 5.40 12-Bit ADC, Linearity Parameters
- 5.41 12-Bit ADC, Temperature Sensor and Built-In VMID
- 5.42 Flash Memory
- 5.43 JTAG and Spy-Bi-Wire Interface
-
6Detailed Description
- 6.1 CPU
- 6.2 Operating Modes
- 6.3 Interrupt Vector Addresses
- 6.4 Memory Organization
- 6.5 Bootloader (BSL)
- 6.6 JTAG Operation
- 6.7 Flash Memory (Link to User's Guide)
- 6.8 RAM (Link to User's Guide)
- 6.9
Peripherals
- 6.9.1 Digital I/O (Link to User's Guide)
- 6.9.2 Oscillator and System Clock (Link to User's Guide)
- 6.9.3 Power-Management Module (PMM) (Link to User's Guide)
- 6.9.4 Hardware Multiplier (Link to User's Guide)
- 6.9.5 Real-Time Clock (RTC_A) (Link to User's Guide)
- 6.9.6 Watchdog Timer (WDT_A) (Link to User's Guide)
- 6.9.7 System Module (SYS) (Link to User's Guide)
- 6.9.8 DMA Controller (Link to User's Guide)
- 6.9.9 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
- 6.9.10 TA0 (Link to User's Guide)
- 6.9.11 TA1 (Link to User's Guide)
- 6.9.12 TB0 (Link to User's Guide)
- 6.9.13 ADC12_A (Link to User's Guide)
- 6.9.14 CRC16 (Link to User's Guide)
- 6.9.15 Embedded Emulation Module (EEM) (L Version) (Link to User's Guide)
- 6.9.16 Peripheral File Map
- 6.10
Input/Output Diagrams
- 6.10.1 Port P1, P1.0 to P1.7, Input/Output With Schmitt Trigger
- 6.10.2 Port P2, P2.0 to P2.7, Input/Output With Schmitt Trigger
- 6.10.3 Port P3, P3.0 to P3.7, Input/Output With Schmitt Trigger
- 6.10.4 Port P4, P4.0 to P4.7, Input/Output With Schmitt Trigger
- 6.10.5 Port P5, P5.0 and P5.1, Input/Output With Schmitt Trigger
- 6.10.6 Port P5, P5.2, Input/Output With Schmitt Trigger
- 6.10.7 Port P5, P5.3, Input/Output With Schmitt Trigger
- 6.10.8 Port P5, P5.4 to P5.7, Input/Output With Schmitt Trigger
- 6.10.9 Port P6, P6.0 to P6.7, Input/Output With Schmitt Trigger
- 6.10.10 Port P7, P7.0, Input/Output With Schmitt Trigger
- 6.10.11 Port P7, P7.1, Input/Output With Schmitt Trigger
- 6.10.12 Port P7, P7.2 and P7.3, Input/Output With Schmitt Trigger
- 6.10.13 Port P7, P7.4 to P7.7, Input/Output With Schmitt Trigger
- 6.10.14 Port P8, P8.0 to P8.7, Input/Output With Schmitt Trigger
- 6.10.15 Port P9, P9.0 to P9.7, Input/Output With Schmitt Trigger
- 6.10.16 Port P10, P10.0 to P10.7, Input/Output With Schmitt Trigger
- 6.10.17 Port P11, P11.0 to P11.2, Input/Output With Schmitt Trigger
- 6.10.18 Port J, J.0 JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
- 6.10.19 Port J, J.1 to J.3 JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
- 6.11 TLV (Device Descriptor) Structures
- 7器件和文檔支持
- 8機械，封裝和可訂購信息
5.33 USCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(see Figure 5-11 and Figure 5-12)
| PARAMETER | TEST CONDITIONS | VCC | MIN | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fUSCI | USCI input clock frequency | SMCLK, ACLK
Duty cycle = 50% ±10% |
fSYSTEM | MHz | ||
| tSU,MI | SOMI input data setup time | 2.2 V | 65 | ns | ||
| 3 V | 50 | |||||
| tHD,MI | SOMI input data hold time | 2.2 V | 0 | ns | ||
| 3 V | 0 | |||||
| tVALID,MO | SIMO output data valid time(2) | UCLK edge to SIMO valid,
CL = 20 pF |
2.2 V | 25 | ns | |
| 3 V | 20 | |||||
| tHD,MO | SIMO output data hold time(3) | CL = 20 pF | 2.2 V | ns | ||
| 3 V | ||||||
(1) fUCxCLK = 1/2 × tLO/HI with tLO/HI ≥ max(tVALID,MO(USCI) + tSU,SI(Slave), tSU,MI(USCI) + tVALID,SO(Slave))
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
For the slave parameters tSU,SI(Slave) and tVALID,SO(Slave), see the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. See the timing diagrams in Figure 5-11 and Figure 5-12.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data on the SIMO output can become invalid before the output changing clock edge observed on UCLK. See the timing diagrams in Figure 5-11 and Figure 5-12.
Figure 5-11 SPI Master Mode, CKPH = 0 
Figure 5-12 SPI Master Mode, CKPH = 1