8.1.1 LMX243x Charge-Pump Test Setup

Figure 23. Charge-Pump Current Test Setup

Figure 23 shows the setup required to measure the RF charge-pump sink current of the LMX243x device. The same setup is used for the LMX2430PW evaluation board. The purpose of this test is to assess the functionality of the RF charge pump. The IF charge pump is evaluated in the same way.

This setup uses an open-loop configuration. A power supply is connected to V_CC. By means of a signal generator, a 10-MHz signal is typically applied to the FinRF pin. The signal is one of two inputs to the phase / frequency detector (PFD). The 3-dB pad provides a 50-Ω match between the PLL and the signal generator. The OSCin pin is tied to Vcc. This establishes the other input to the PFD. Alternatively, this input can be tied directly to the ground plane. The EN and ENosc pins are also both tied to Vcc. A semiconductor parameter analyzer is connected to the CPoutRF pin and used to measure the sink, source, and tri-state leakage currents.

Let F_r represent the frequency of the signal applied to the OSCin pin, which is simply zero in this case (DC), and let F_p represent the frequency of the signal applied to the FinRF pin. The PFD is sensitive to the rising edges of F_r and F_p. Assuming positive VCO characteristics (RF_CPP bit = 1); the charge pump turns ON, and sinks current when the first rising edge of F_p is detected. Because F_r has no rising edge, the charge pump continues to sink current indefinitely. In order to measure the RF charge-pump source current, the RF_CPP bit is simply set to 0 (negative VCO characteristics) in CodeLoader. Similarly, in order to measure the tri-state leakage current, the RF_CPT bit is set to 1.

The measurements are typically taken over supply voltage and temperature. The measurements are also typically taken at the HIGH and LOW charge-pump current gains. The charge-pump current gain can be controlled by the RF_CPG bit in CodeLoader. Once the charge-pump currents are determined, the (i) charge-pump output current magnitude variation versus charge-pump output voltage, (ii) charge-pump output sink current versus charge-pump output source current mismatch, and (iii) charge-pump output current magnitude versus temperature, can be calculated. Refer to the Charge Pump Current Specifications Definition for more details.

8.1.2 Charge-Pump Current Specification Definitions

I1 = Charge-Pump Sink Current at V_CPout = Vcc − ΔV
I2 = Charge-Pump Sink Current at V_CPout = Vcc//2
I3 = Charge-Pump Sink Current at V_CPout = ΔV
I4 = Charge-Pump Source Current at V_CPout = Vcc − ΔV
I5 = Charge-Pump Source Current at V_CPout = Vcc/2
I6 = Charge-Pump Source Current at V_CPout = ΔV
ΔV = Voltage offset from the positive and negative rails. Dependent on the VCO tuning range relative to Vcc and GND. Typical values are between 0.5V and 1.0V.
V_CPout refers to either V_CPoutRF or V_CPoutIF
I_CPout refers to either I_CPoutRF or I_CPoutIF

Figure 24. Charge-Pump Parameters

8.1.2.1 Charge-Pump Output Current Variation vs Charge-Pump Output Voltage

Equation 1.

8.1.2.2 Charge-Pump Sink Current vs Charge-Pump Output Source Current Mismatch

Equation 2.

8.1.2.3 Charge-Pump Output Current Variation vs Temperature

Equation 3.

8.1.3 LMX243x FinRF Sensitivity Test Setup

Figure 25. RF Input Sensitivity Test Setup

Figure 25 shows the setup required to measure the RF input sensitivity level of the LMX243x device. The same setup is used for the LMX2430PW evaluation board. The purpose of this test is to measure the acceptable signal level to the FinRF input of the PLL chip. Outside the acceptable signal range, the feedback divider begins to divide incorrectly and miscount the frequency. The FinIF sensitivity is evaluated in the same way.

The setup uses an open-loop configuration. A power supply is connected to Vcc. The IF PLL is powered down (IF_PD bit = 1). By means of a signal generator, an RF signal is applied to the FinRF pin. The 3-dB pad provides a 50-Ω match between the PLL and the signal generator. The EN, ENosc, and OSCin pins are all tied to V_CC. The N value is typically set to 10000 in CodeLoader, that is, RF_B word = 156 and RF_A word = 16 for RF_P bit = 0 (LMX2434) or RF_P bit = 1 (LMX2430 and LMX2433). The feedback divider output is routed to the Ftest/LD pin by selecting the RF_N/2 Frequency word (MUX[3:0] word = 15) in CodeLoader. A Universal Counter is connected to the Ftest/LD pin and used to monitor the output frequency of the feedback divider. The expected frequency must be the signal generator frequency divided by twice the corresponding counter value, that is, 20,000. The factor of two comes in because the LMX43x device has an internal /2 circuit which is used to provide a 50% duty cycle.

Sensitivity is typically measured over frequency, supply voltage and temperature. In order to perform the measurement, the temperature, frequency, and supply voltage is set to a fixed value, and the power level of the signal at FinRF is varied. Sensitivity is reached when the frequency error of the divided RF input is greater than or equal to 1 Hz. The power attenuation from the cable and the 3-dB pad must be accounted for. The feedback divider miscounts if too much or too little power is applied to the FinRF input. Therefore, the allowed input power level is bounded by the upper and lower sensitivity limits. In a typical application, if the power level to the FinRF input approaches the sensitivity limits, this can introduce spurs or cause degradation to the phase noise. When the power level gets even closer to these limits, or exceeds them, the RF PLL loses lock.

8.1.4 LMX243x OSCin Sensitivity Test Setup

Figure 26. OSCin Sensitivity Test Setup

Figure 26 shows the setup required to measure the OSCin buffer sensitivity level in the LMX243x device. The same setup is used for the LMX2430PW evaluation board. This setup is similar to the FinRF sensitivity setup except that the signal generator is now connected to the OSCin pin, and both Fin pins are tied to V_CC. The 51-Ω shunt resistor matches the OSCin input to the signal generator. The R counter is typically set to 1000, that is, RF_R word = 1000 or IF_R word = 1000. The reference divider output is routed to the Ftest/LD pin by selecting the RF_R/ 2 frequency word (MUX[3:0] word = 14) or the IF_R/ 2 frequency word (MUX[3:0] word = 12) in CodeLoader. A universal counter is connected to the Ftest/LD pin and is used to monitor the output frequency of the reference divider. The expected frequency must be the signal generator frequency divided by twice the corresponding counter value, that is, 2000. The factor of two comes in because the LMX243x device has an internal /2 circuit which is used to provide a 50% duty cycle.

In a similar way, sensitivity is typically measured over frequency, supply voltage and temperature. In order to perform the measurement, the temperature, frequency, and supply voltage is set to a fixed value and the power level (voltage level) of the signal at OSCin is varied. Sensitivity is reached when the frequency error of the divided input signal is greater than or equal to 1 Hz.

8.1.5 LMX243x FinRF Input Impedance Test Setup

Figure 27. Imput Impedance Test Setup

    Notes:
    1.  DATA is clocked into the 24-bit shift register on the rising edge of CLK
    2.  The MSB of DATA is shifted in first.

Figure 28. LMX243x Serial Data Input Timing

Figure 28 shows the setup required to measure the RF input impedance of the LMX243x device. The same setup is used for the LMX2430PW evaluation board. Measuring the input impedance of the device facilitates the design of appropriate matching networks to match the PLL to the VCO, or in more critical situations, to the characteristic impedance of the printed-circuit-board (PCB) trace, to prevent undesired transmission line effects. The FinIF input impedance is evaluated in the same way.

Before the actual measurements are taken, the network analyzer must be calibrated, that is, the error coefficients must be calculated. The calibration standard of the network analyzer is used to calculate these coefficients. The calibration standard includes an open, short and a matched load. A 1-port calibration is implemented here.

To calculate the coefficients, the PLL chip is first removed from the PCB. A piece of semi-rigid coaxial cable is then soldered to the pad on the PCB which is equivalent to the FinRF pin on the PLL chip. Proper grounding near the exposed tip of the semi-rigid coaxial cable is required for accurate results. The DC blocking capacitor is removed for this test. The network analyzer port is then connected to the other end of the semi-rigid coaxial cable. In this way, the semi-rigid coaxial cable acts as a transmission line. This transmission line adds electrical length and produces an offset from the reference plane of the network analyzer; therefore, it must be included in the calibration. The desired operating frequency is then set. The typical frequency range selected for the RF synthesizer of the LMX243x device is from 100 MHz to 6000 MHz.

The network analyzer calculates the calibration coefficients based on the measured S₁₁ parameters. With this all done, calibration is now complete.

The PLL chip is then placed on the PCB, and a power supply connected to V_CC. The EN, ENosc, and OSCin pins are all tied to V_CC. Alternatively, the OSCin pin can be tied to ground. In this setup, the complementary input (FinRF*) is AC-coupled to ground. With the network analyzer still connected to the semi-rigid coaxial cable, the measured FinRF impedance is displayed.

The OSCin input impedance is measured in the same way. The impedance is measured when the oscillator buffer is powered up (ENosc is set HIGH) and when the oscillator buffer is powered down (ENosc pin is set LOW).

Table 1. LMX243x ULGA FinRF Input Impedance Table⁽¹⁾

Table 2. LMX243x TSSOP FinRF Input Impedance Table⁽¹⁾

Table 3. LMX243x ULGA FinIF Input Impedance Table⁽¹⁾

Table 4. LMX243x TSSOP FinIF Input Impedance Table⁽¹⁾

Table 5. LMX243x ULGA OSCin Input Impedance Table⁽¹⁾

Table 6. LMX243x TSSOP OSCin Input Impedance Table⁽¹⁾