8.2.1 Typical Fully Differential Application

In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 45 illustrates a typical application circuit where an LMH6552 is used to produce a differential signal from a single ended source.

Figure 39. Typical Fully Differential Application Schematic

8.2.1.2 Detailed Design Procedure

To match the input impedance of the circuit in Figure 45 to a specified source resistance, RS, requires that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provided in Figure 45. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50-Ω environment are given in Table 1. Gain Component Values for 50-Ω System WSON Package. Typically RS=50 Ω and RM=RS||RT.

8.2.1.2.1 WSON Package

Due to its size and lower parasitics, the WSON requires the lower optimum value of 275 Ω for R_F. This gives a flat frequency response with minimal peaking. With a lower R_F value the WSON package has a reduction in noise compared to the SOIC with its optimum R_F = 360 Ω.

8.2.1.2.2 Fully Differential Operation

The LMH6552 performs best in a fully differential configuration. The circuit illustrated in Figure 39 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain A_V = V_OUT/ V_IN = R_F/R_G, where the feedback is symmetric. The series output resistors, R_O, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to Driving Capacitive Loads for details.

When driven from a differential source, the LMH6552 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors R_F, R_G and R_O are well matched and strict symmetry is observed in board layout. With an intrinsic device CMRR of 80 dB, using 0.1% resistors gives a worst case CMRR of around 60 dB for most circuits.

The circuit configuration illustrated in Figure 40 was used to measure differential S parameters in a 50-Ω environment at a gain of 1 V/V. Refer to Figure 34 and Figure 35 in the Typical Characteristics for measurement results.

Figure 40. Differential S-Parameter Test Circuit

Table 1. Gain Component Values for 50Ω System WSON Package

Gain	RF	RG	RT	RM
0 dB	275Ω	255Ω	59Ω	26.7Ω
6 dB	275Ω	127Ω	68.1Ω	28.7Ω
12 dB	275Ω	54.9Ω	107Ω	34Ω

Figure 41. Single Ended Input S-Parameter Test Circuit (50Ω System)

The circuit shown in Figure 41 was used to measure S-parameters for a single-to-differential configuration. Figure 34 and Figure 35 in Typical Characteristics are taken using the recommended component values for 0 dB gain.

8.2.1.2.3 Driving Capacitive Loads

As noted previously, capacitive loads must be isolated from the amplifier output with small valued resistors. This is particularly the case when the load has a resistive component that is 500 Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000 Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using matching resistors is sufficient to isolate any subsequent capacitance.

8.2.1.2.3.1 Balanced Cable Driver

With up to 15 V_PP differential output voltage swing and 80 mA of linear drive current the LMH6552 makes an excellent cable driver as illustrated in Figure 42. The LMH6552 is also suitable for driving differential cables from a single ended source.

Figure 42. Fully Differential Cable Driver

8.2.1.3 Application Curves

Many application circuits have capacitive loading. As shown in Figure 43 amplifier bandwidth is reduced with increasing capacitive load, so parasitic capacitance must be strictly limited.

In order to ensure stability resistance must be added between the capacitive load and the amplifier output pins. The value of the resistor is dependent on the amount of capacitive load as shown in Figure 44. This resistive value is a suggestion. System testing is required to determine the optimal value. Using a smaller resistor retains more system bandwidth at the expense of overshoot and ringing, and larger values of resistance reduce overshoot but also reduce system bandwidth.

Figure 43. Frequency Response vs Capacitive Load

Figure 44. Suggested R_OUT vs Capacitive Load

8.2.2 Single-Ended Input to Differential Output Operation

In many applications, it is required to drive a differential input ADC from a single-ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6552 provides excellent performance as a single-to-differential converter down to DC. Figure 45 shows a typical application circuit where an LMH6552 is used to produce a differential signal from a single-ended source.

Figure 45. Single-Ended Input with Differential Output

When using the LMH6552 in single-to-differential mode, the complementary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6552 over frequency is shown in the Typical Characteristics.

To match the input impedance of the circuit in Figure 45 to a specified source resistance, R_S, requires that R_T || R_IN = R_S. The equations governing R_IN and A_V for single-to-differential operation are also provided in Figure 45. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configurations in a 50-Ω environment are given in Table 1. Typically R_S=50Ω and R_M=R_S||R_T.

8.2.3 Single Supply Operation

Single supply operation is possible on supplies from 5 V to 10 V; however, as discussed earlier, AC input coupling is recommended for low supplies such as 5 V due to input common mode limitations. An example of an AC coupled, single supply, single-to-differential circuit is illustrated in Figure 46. Note that when AC coupling, both inputs need to be AC coupled irrespective of single-to-differential or differential-to-differential configuration. For higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operating ranges.

Figure 46. AC Coupled for Single Supply Operation

8.2.4 Split Supply Operation

For optimum performance, split supply operation is recommended using +5 V and −5 V supplies; however, operation is possible on split supplies as low as +2.25 V and −2.25 V and as high as +6 V and −6 V. Provided the total supply voltage does not exceed the 4.5-V to 12-V operating specification, non-symmetric supply operation is also possible and in some cases advantageous. For example, if a 5-V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V⁺) and (V⁻). Where (V⁺) - (V⁻) = 5V and V⁺ and V⁻ are selected to center the amplifier input common mode range to suit the application.

Figure 47. Split Supply

8.2.5 Output Noise Performance and Measurement

Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6552 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6552 at much higher gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor.

Figure 48 shows a circuit configuration used to measure noise figure for the LMH6552 in a 50-Ω system. An R_F value of 275 Ω is chosen for the SOIC package to minimize output noise and simultaneously allows both high gain (9 V/V) and proper 50-Ω input termination. Refer to Single-Ended Input to Differential Output Operation for calculation of resistor and gain values. Noise figure values at various frequencies are shown Figure 31 in the Typical Characteristics.

Figure 48. Noise Figure Circuit Configuration

8.2.6 Driving Analog to Digital Converters

Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. As well, there are usually current spikes associated with switched capacitor or sample and hold circuits. Figure 49 shows a combination circuit of the LMH6552 driving the ADC12DL080. The two 125-Ω resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the resistors, along with a 2.2-pF capacitor across the outputs (in parallel with the ADC input capacitance), form a low pass anti-aliasing filter with a pole frequency of about 60 MHz. For switched capacitor input ADCs, the input capacitance varies based on the clock cycle, as the ADC switches between the sample and hold mode. See your particular ADC's datasheet for details.

Figure 49. Driving a 12-Bit ADC

Figure 50 illustrates the SFDR and SNR performance vs frequency for the LMH6552 and ADC12DL080 combination circuit with the ADC input signal level at −1 dBFS. The ADC12DL080 is a dual 12-bit ADC with maximum sampling rate of 80 MSPS. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external band-pass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. In order to properly match the input impedance seen at the LMH6552 amplifier inputs, R_M is chosen to match Z_S || R_T for proper input balance.

Figure 50. LMH6552/ADC12DL080 SFDR and SNR Performance vs. Frequency

Figure 51 shows a combination circuit of the LMH6552 driving the ADC14DS105. The ADC14DS105 is a dual channel 14-bit ADC with a sampling rate of 105 MSPS. The circuit in Figure 51 has a 2nd order low-pass LC filter formed by the 620 nH inductor along with the 22-pF capacitor across the differential outputs of the LMH6552. The filter has a pole frequency of about 50 MHz. Figure 52 shows the combined SFDR and SNR performance over frequency with a −1 dBFs input signal and a sampling rate of 1000 MSPS.

Figure 51. Driving a 14-bit ADC

The amplifier is configured to provide a gain of 2 V/V in a single-to-differential mode. The LMH6552 common mode voltage is set by the ADC14DS105. Circuit testing is the same as described for the LMH6552 and ADC12DL080 combination circuit. The 0.1-µF capacitor, in series with the 49.9-Ω resistor, is inserted to ground across the 68.1Ω-resistor to balance the amplifier inputs.

Figure 52. LMH6552/ADC14DS105 SFDR and SNR Performance vs. Frequency

The amplifier and ADC must be located as close as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output traces and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2).

The LMH6552 is capable of driving a variety of Texas Instruments Analog-to-Digital Converters. This is shown in Table 2, which offers a list of possible signal path ADC and amplifier combinations. The use of the LMH6552 to drive an ADC is determined by the application and the desired sampling process (Nyquist operation, sub-sampling or over-sampling). See application note AN-236 for more details on the sampling processes and application note AN-1393 'Using High Speed Differential Amplifiers to Drive ADCs. For more information regarding a particular ADC, refer to the particular ADC datasheet for details.