SNVSCU3 October 2025 LM5137
PRODMIX
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| INPUT SUPPLY (VIN) | ||||||
| IQ-SHDN | VIN shutdown current | VEN1 = VEN2 = 0V | 3.6 | μA | ||
| IQ-SHDN-48V | VIN shutdown current | VEN1 = VEN2 = 0V, VIN = 48V | 6 | μA | ||
| IQ-STBY | VIN standby current | 0.6V < VEN1/2 < 1V | 260 | μA | ||
| IQ-SLEEP | VIN sleep current, VVOUT1 = 5V, VVOUT2 = 3.3V | 1.05V ≤ VEN1/2 ≤ VIN, VVOUT1 = 5V, VVOUT2 = 3.3V, in regulation at no load, not switching, VPFM/SYNC = 5V | 1.5 | μA | ||
| IQ-SLEEP-48V | VIN sleep current, VVOUT1 = 5V, VVOUT2 = 3.3V, VIN = 48V | 1.05V ≤ VEN1/2 ≤ VIN, VVOUT1 = 5V, VVOUT2 = 3.3V, in regulation, no load, not switching,VPFM/SYNC = 5V, VIN = 48V | 3.1 | μA | ||
| INTERNAL LDO (VCC) | ||||||
| VVCC-REG | VCC regulation voltage | IVCC = 0mA | 4.8 | 5.0 | 5.2 | V |
| VVCC-UVLO | VCC UVLO rising threshold | 3.7 | 3.8 | 3.9 | V | |
| VVCC-UVLO-HYST | VCC UVLO hysteresis | 300 | mV | |||
| IVCC-REG | VCC short-circuit current limit | 175 | 300 | mA | ||
| INTERNAL LDO (VDDA) | ||||||
| VVDDA-REG | VDDA regulation voltage | 5 | V | |||
| RVDDA | VDDA resistance to VCC | 12 | ? | |||
| EXTERNAL BIAS (BIAS1) | ||||||
| VBIAS-ON | VBIAS1/VOUT1 rising | 4.1 | 4.3 | 4.5 | V | |
| VBIAS-HYST | Bias hysteresis voltage | 130 | mV | |||
| REFERENCE VOLTAGE (FB1, FB2) | ||||||
| VREF1 | Regulated FB voltage | 792 | 800 | 808 | mV | |
| PRECISION ENABLE (EN1, EN2) | ||||||
| VSDN1/2 | Shutdown-to-standby threshold | VEN1/2 rising | 0.6 | V | ||
| VEN1/2-HIGH | Enable voltage rising threshold | VEN1/2 rising, switching enabled | 0.95 | 1.0 | 1.05 | V |
| VEN1/2-HYS | Enable hysteresis voltage | 50 | mV | |||
| IEN1/2-HYS | Enable hysteresis current | VEN1/2 = 1.1V | –12 | –10 | –8 | μA |
| OUTPUT VOLTAGE (VOUT1/BIAS1, VOUT2) | ||||||
| VOUT1/2-3.3V | 3.3V fixed output setpoint | RFB1/2 = 7.5k?, 4V ≤ VVIN ≤ 80V | 3.267 | 3.3 | 3.33 | V |
| VOUT1/2-5V | 5V fixed output setpoint | RFB1/2 = 24.9k? | 4.95 | 5 | 5.05 | V |
| VOUT1/2-12V | 12V fixed output setpoint | RFB1/2 = 48.7k?, 13V ≤ VVIN ≤ 80V | 11.82 | 12 | 12.18 | V |
| ERROR AMPLIFIER (COMP1, COMP2) | ||||||
| gm1/2 | EA transconductance | ΔVFB1/2 ± 50mV | 400 | 600 | μS | |
| VCOMP1/2-CLAMP | COMP clamp voltage | VFB1/2 = 0V | 1.75 | V | ||
| ICOMP1/2-SRC | EA source current | VCOMP1/2 = 1V, VFB1/2 = 0.6V | 120 | μA | ||
| ICOMP1/2-SINK | EA sink current | VCOMP1/2 = 1V, VFB1/2 = 1V | 120 | μA | ||
| VDRIVER1/2-DISABLE | COMP threshold voltage below which the driver is disabled | 100 | mV | |||
| POWER GOOD (PG1, PG2) | ||||||
| VPG1/2-OV | PG1/2 overvoltage | Rising threshold | 103 | 105 | 107 | % |
| VPG1/2-OV-HYST | PG1/2 OV hysteresis | 1 | % | |||
| VPG1/2-UV | PG1/2 undervoltage | Falling threshold | 93 | 95 | 97 | % |
| VPG1-UV-HYST | PG1/2 UV hysteresis | 1 | % | |||
| t-PG1/2-DEGLITCH(R) | PG1/2 deglitch rising | 1.4 | 2 | 2.6 | ms | |
| t-PG1/2-DEGLITCH(F) | PG1/2 deglitch falling | 60 | 90 | 120 | μs | |
| RPG1/2(on) | PG1/2 on resistance | Open drain, IPG1/2 = 250μA | 100 | 250 | ? | |
| SWITCHING FREQUENCY (RT) | ||||||
| FSW1 | Switching frequency 1 | RRT = 100k? to AGND | 230 | kHz | ||
| FSW2 | Switching frequency 2 | RRT = 10k? to AGND | 1.98 | 2.2 | 2.42 | MHz |
| FSW3 | Switching frequency 3 | RRT = 230k? to AGND | 100 | kHz | ||
| SLOPE1 | Internal slope compensation 1 | RRT = 10k? to AGND | 500 | mV/μs | ||
| SLOPE2 | Internal slope compensation 2 | RRT = 100k? to AGND | 42 | mV/μs | ||
| tON(min) | PWM minimum on-time | 22 | 35 | ns | ||
| tOFF(min) | PWM minimum off-time | Measured at nominal frequency, before the frequency folds back to achieve 100% duty cycle | 45 | ns | ||
| DMAX | Maximum duty cycle | 100 | % | |||
| SYNCHRONIZATION OUTPUT (SYNCOUT) | ||||||
| VSYNCOUT-HO | SYNCOUT high-state voltage | ISYNCOUT = –4mA | 2 | V | ||
| VSYNCOUT-LO | SYNCOUT low-state voltage | ISYNCOUT = 4mA | 0.8 | V | ||
| tSYNCOUT1 | Delay from HO1 rising edge to SYNCOUT rising edge | VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230k? | 2.5 | μs | ||
| tSYNCOUT2 | Delay from HO1 rising edge to SYNCOUT falling edge | VPFM/SYNC = 0V, TS = 1/FSW, FSW set by RRT = 230k? | 7.5 | μs | ||
| PULSE FREQUENCY MODULATION and SYNCHRONIZATION INPUT (PFM/SYNC) | ||||||
| VPFM-LO | PFM detection threshold low | 0.8 | V | |||
| VPFM-HI | PFM detection threshold high | 1.2 | V | |||
| VZC-SW | Zero-cross detection threshold | –5.5 | mV | |||
| FSYNCIN | Frequency synchronization range | RRT = 10k?, ±20% of the nominal oscillator frequency | 1760 | 2640 | kHz | |
| tSYNC-MIN | Minimum pulsewidth of external synchronization | 20 | ns | |||
| tSYNCIN-HO | Delay from PFM/SYNC rising edge to HO1 rising edge | 90 | ns | |||
| tPFM-FILTER | SYNCIN to PFM mode | 14 | 70 | μs | ||
| BOOTSTRAP CIRCUIT (CBOOT1, CBOOT2) | ||||||
| VBOOT1/2-DROP | Internal diode forward drop | ICBOOT1/2 = 20mA, VCC to CBOOT1/2 | 0.8 | V | ||
| IBOOT1/2 | CBOOT-to-SW quiescent current, not switching | VEN1/2 = 5V, VCBOOT1/2 – VSW1/2 = 5V | 2 | μA | ||
| VBOOT1/2-SW-UV-R | CBOOT-to-SW UVLO rising threshold | VCBOOT1/2 – VSW1/2 rising | 2.7 | V | ||
| VBOOT1/2-SW-UV-F | CBOOT-to-SW UVLO falling threshold | VCBOOT1/2 – VSW1/2 falling | 2.47 | V | ||
| VCHARGE–PUMP1/2-UNLOADED | Charge pump output voltage | ICBOOT1/2 = 0μA | 4.8 | V | ||
| ICHARGE–PUMP1/2 | Charge pump output current | VCBOOT1/2 = 3.5V | 20 | μA | ||
| HIGH-SIDE GATE DRIVER (HO1, HO2) | ||||||
| VHO1/2-HIGH | HO1/2 high-state output voltage | IHO1/2 = –100mA | 95 | mV | ||
| VHO1/2-LOW | HO1/2 low-state output voltage | IHO1/2 = 100mA | 43 | mV | ||
| IHO1/2-SRC | HO1/2 peak source current | VHO1/2 = VSW1/2 = 0V | 2 | A | ||
| IHO1/2-SINK | HO1/2 peak sink current | VCBOOT1/2 – VSW1/2 = 5V | 3 | A | ||
| LOW-SIDE GATE DRIVER (LO1, LO2) | ||||||
| VLO1/2-HIGH | LO1/2 high-state output voltage | ILO1/2 = –100mA | 100 | mV | ||
| VLO1/2-LOW | LO1/2 low-state output voltage | ILO1/2 = 100mA | 58 | mV | ||
| ILO1/2-SRC | LO1/2 peak source current | VLO1/2 = 0V | 2 | A | ||
| ILO1/2-SINK | LO1/2 peak sink current | VVCC = 5V | 3 | A | ||
| ADAPTIVE DEADTIME CONTROL | ||||||
| tDEAD1 | HO1/2 off to LO1/2 deadtime | 20 | ns | |||
| tDEAD2 | LO1/2 off to HO1/2 on deadtime | 20 | ns | |||
| START-UP (RSS) | ||||||
| RSS1 | 1.5ms soft-start time | RSS1 = 0? | 1.5 | ms | ||
| RSS2 | 2ms soft-start time | RSS2 = 8.06k? | 2 | ms | ||
| RSS3 | 20ms soft-start time | RSS3 = 95.3k? | 20 | ms | ||
| DUAL RANDOM SPREAD SPECTURM (DRSS) | ||||||
| fm | Modulation frequency | 7.2 | 12 | 16.8 | kHz | |
| ΔfSS1/2-LF | Low-frequency triangular spread spectrum modulation range1 maximum | RCNFG = 19.1k? or 54.9k? | –5 | 5 | % | |
| ΔfSS2-LF | Low-frequency triangular spread spectrum modulation range2 maximum | RCNFG = 29.4k? or 71.5k? | –10 | 10 | % | |
| OVERCURRENT PROTECTION (ISNS1+, ISNS2+) | ||||||
| VCS1/2-TH | Current limit threshold | Measured from ISNS1/2+ to VOUT1/2 | 54 | 60 | 66 | mV |
| tDELAY1/2-ISNS+ | ISNS+ delay from VCS-TH to HO off | 48 | ns | |||
| GCS1/2 | CS amplifier gain | 9.5 | 10 | 10.5 | V/V | |
| VCS-SHARE | COMP to current accuracy | VCOMP1/2 = 1.2V | 54 | 60 | 66 | mV |
| INTERNAL HICCUP MODE | ||||||
| HICDLY | Hiccup-mode activation delay | VISNS1/2+ – VVOUT1/2 > 60mV | 512 | cycles | ||
| HICTIME | Hiccup-mode duration | VISNS1/2+ – VVOUT1/2 > 60mV | 16384 | cycles | ||
| THERMAL SHUTDOWN | ||||||
| TSHD | Thermal shutdown threshold | Temperature rising | 175 | °C | ||
| TSHD-HYS | Thermal shutdown hysteresis | 15 | °C | |||