7.3.8 HO and LO Drivers

The LM5122ZA contains strong N-channel MOSFET gate drivers and an associated high-side level shifter to drive the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external boot diode D_BST, and bootstrap capacitor C_BST. During the on-time of the low-side N-channel MOSFET driver, the SW pin voltage is approximately 0 V, and the C_BST is charged from VCC through the D_BST. TI recommends a 0.1-μF or larger ceramic capacitor, connected with short traces between the BST and SW pin.

The LO and HO outputs are controlled with an adaptive dead-time methodology which insures that both outputs are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO fall to LO rise delay). Similarly, the HO turnon is delayed until the LO voltage has discharged. HO is then enabled after a small delay (LO fall to HO rise delay). This technique insures adequate dead-time for any size N-channel MOSFET device, especially when VCC is supplied by a higher external voltage source. Be careful when adding series gate resistors, as this may decrease the effective dead time.

Exercise care when selecting the N-channel MOSFET devices threshold voltage, especially if the VIN voltage range is below the VCC regulation level or a bypass operation is required. If the bypass operation is required, especially when output voltage is less than 12 V, select a logic level device for the high-side N-channel MOSFET. During start-up at low input voltages, the low-side N-channel MOSFET switch gate plateau voltage must be sufficient to completely enhance the N-channel MOSFET device. If the low-side N-channel MOSFET drive voltage is lower than the low-side N-channel MOSFET device gate plateau voltage during startup, the regulator may not start up properly and it may stick at the maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET switch or by increasing V_IN(STARTUP) with the UVLO pin voltage programming.