7.3.1 Undervoltage Lockout (UVLO)

The LM5121 features a dual level UVLO circuit. When the UVLO pin voltage is less than the 0.4-V UVLO standby threshold, the LM5121 is in the shutdown mode with all functions disabled. The shutdown comparator provides 0.1 V of hysteresis to avoid chatter during transitions. If the UVLO pin voltage is greater than 0.4 V and below 1.2 V during power up, the controller is in the standby mode with the VCC regulator operational, the disconnection switch disabled and no switching at the HO and LO outputs. This feature allows the UVLO pin to be used as a remote shutdown function by pulling the UVLO pin down below the UVLO standby threshold with an external open collector or open drain device.

Figure 18. UVLO Remote Standby and Shutdown Control

If the UVLO pin voltage is above 1.2-V UVLO threshold and VCC voltage exceeds the VCC UV threshold, the startup sequence begins. UVLO hysteresis is accomplished with an internal 10-μA current source that is switched on or off into the impedance of the UVLO setpoint divider. When the UVLO pin voltage exceeds the 1.2 V, the current source is enabled to quickly raise the voltage at the UVLO pin. When the UVLO pin voltage falls below the 1.2-V UVLO threshold, the current source is disabled causing the voltage at the UVLO pin to quickly fall. In addition to the UVLO hysteresis current source, a 5-μs deglitch filter on both rising and falling edge of UVLO toggling helps preventing chatter during power up or down.

An external UVLO setpoint voltage divider from the supply voltage to AGND is used to set the minimum input operating voltage of the regulator. The divider must be designed such that the voltage at the UVLO pin is greater than 1.2 V when the input voltage is in the desired operating range. The maximum voltage rating of the UVLO pin is 16 V. If necessary, the UVLO pin can be clamped with an external zener diode. The UVLO pin should not be left floating. The values of R_UV1 and R_UV2 can be determined from Equation 1 and Equation 2.

Equation 1.

Equation 2.

where

• V_HYS is the desired UVLO hysteresis
• V_IN(STARTUP) is the desired startup voltage of the regulator during turn-on.

Typical shutdown voltage during turn-off can be calculated as follows:

Equation 3.

7.3.2 High Voltage VCC Regulator

The LM5121 contains an internal high voltage regulator that provides typical 7.6-V VCC bias supply for the controller and N-channel MOSFET drivers. The input of the VCC regulator, VIN can be connected to a voltage source as high as 65 V. The VCC regulator turns on when the UVLO pin voltage is greater than 0.4 V. When the input voltage is below the VCC setpoint level, the VCC output tracks VIN with a small dropout voltage. The output of the VCC regulator is current limited at 50-mA minimum.

Upon power-up, the VCC regulator sources current into the capacitor connected to the VCC pin. The recommended range for the VCC capacitor is 1.0 μF to 47 μF and it is recommended to be at least 10 times greater than C_BST value. When operating with a VIN voltage less than 6 V, the value of VCC capacitor should be 4.7 µF or greater.

The internal power dissipation of the LM5121 device can be reduced by supplying VCC from an external supply. If an external VCC bias supply exists and the voltage is greater than 9 V and below 14.5 V. The external VCC bias supply can be applied to the VCC pin directly through a diode, as shown in Figure 19.

Figure 19. External Bias Supply when 9 V < V_EXT< 14.5 V

Shown in Figure 20 is a method to derive the VCC bias voltage with an additional winding on the boost inductor. This circuit must be designed to raise the VCC voltage above VCC regulation voltage to shut off the internal VCC regulator.

Figure 20. External Bias Supply using Transformer

The VCC regulator series pass transistor includes a diode between VCC and VIN, as shown in Figure 21, that should not be forward biased in normal operation. If the voltage of the external VCC bias supply is greater than the VIN pin voltage, an external blocking diode is required from the input power supply to the VIN pin to prevent the external bias supply from passing current to the input supply through VCC. The need for the blocking diode should be evaluated for all applications when the VCC is supplied by the external bias supply. When the input power supply voltage is less than 4.5 V, an external VCC supply should be used and the external blocking diode is required.

Figure 21. VIN Configuration when V_VIN<V_VCC

7.3.3 Oscillator

The LM5121 switching frequency is programmable by a single external resistor connected between the RT pin and the AGND pin. The resistor should be located very close to the device and connected directly to the RT and AGND pin. To set a desired switching frequency (f_SW), the resistor value can be calculated from Equation 4.

Equation 4.

7.3.4 Slope Compensation

For duty cycles greater than 50%, peak current mode regulators are subject to sub-harmonic oscillation. Sub-harmonic oscillation is normally characterized by alternating wide and narrow duty cycles. This sub-harmonic oscillation can be eliminated by a technique, which adds an artificial ramp, known as slope compensation, to the sensed inductor current.

Figure 22. Slope Compensation

The slope compensation of the LM5121 is programmable by a single resistor connected between the SLOPE pin and the AGND pin. The amount of slope compensation can be calculated as follows:

Equation 5.

where

• 

R_SLOPE value can be determined from the following equation at minimum input voltage:

Equation 6.

where

• K=0.82~1 as a default

From the above equation, K can be calculated over the input range as follows:

Equation 7.

where

• 

In any case, K should be greater than 0.5. At higher switching frequency over 500 kHz, the K factor is recommended to be greater than or equal to 1 because the minimum on-time affects the amount of slope compensation due to internal delays.

The sum of sensed inductor current and slope compensation should be less than COMP output high voltage (V_OH) for proper startup with load and proper current limit operation. This limits the minimum value of R_SLOPE to be:

Equation 8.

where

• This equation can be used in most cases

where
• This conservative selection should be considered when V_IN(MIN) < 5.5 V

The SLOPE pin cannot be left floating.

7.3.5 Error Amplifier

The internal high-gain error amplifier generates an error signal proportional to the difference between the FB pin voltage and the internal precision 1.2-V reference. The output of the error amplifier is connected to the COMP pin allowing the user to provide a Type 2 loop compensation network.

R_COMP, C_COMP and C_HF configure the error amplifier gain and phase characteristics to achieve a stable voltage loop. This network creates a pole at DC, a mid-band zero (f_{Z_EA}) for phase boost, and a high frequency pole (f_{P_EA}). The minimum recommended value of R_COMP is 2 kΩ (See the Feedback Compensation section).

Equation 9.

Equation 10.

7.3.6 PWM Comparator

The PWM comparator compares the sum of sensed inductor current and slope compensation ramp to the voltage at the COMP pin through a 1.2-V internal COMP to PWM voltage drop and terminates the present cycle when the sum of sensed inductor current and slope compensation ramp is greater than V_COMP –1.2 V.

Figure 23. Feedback Configuration and PWM Comparator

7.3.7 Disconnection Switch Control

Soft turn-on is achieved by slowly turning on the disconnection switch. When the UVLO pin voltage is greater than 1.2-V UVLO threshold and the VCC voltages exceeds the VCC UV threshold, the internal charge pump at DG starts sourcing current which enhances N-channel MOSFET disconnection switch. The internal charge pump provides bias voltage at DG pin above VIN pin voltage.

Additional inrush current limiting helps to limit the maximum inrush current. In the inrush current limiting condition when the voltage across sense resistor R_S reaches the inrush current limit threshold, the DG pin voltage is controlled to limit the current flow in R_S by controlling DG pull-down current sink.

As the source voltage of the disconnection switch is charged during initial charging period, the operating point of the disconnection switch transitions from an active region into the ohmic region and the DG pin voltage is maintained by the charge pump. An internal 10 µA soft-start current source turns on when the DG to DS voltage is greater than V_GS detection threshold. VIN voltage is recommended to be greater than or equal to the input power supply voltage because the internal charge pump provides the DG bias voltage above the VIN voltage.

The DG pin voltage is clamped to approximately 16 V above the DS pin and 11 V above the VIN pin by internal zener diodes.

Figure 24. Start-Up Sequence

7.3.8 Soft-Start

The soft-start feature helps the regulator gradually reach the steady state operating point, thus reducing startup stresses and surges. The LM5121 regulates the FB pin to the SS pin voltage or the internal 1.2-V reference, whichever is lower. The internal 10-μA soft-start current source gradually increases the voltage on an external soft-start capacitor connected to the SS pin. This results in a gradual rise of the output voltage starting from the input voltage level to the target output voltage. The soft-start time (t_SS) varies with the input supply voltage and output set point and is calculated from Equation 11.

Equation 11.

When UVLO pin voltage is greater than 1.2–V UVLO threshold, VCC voltage exceeds the VCC UV threshold and DG to DS voltage is greater than V_GS detection threshold, an internal 10-μA soft-start current source turns on. At the beginning of this soft-start sequence, V_SS should be allowed to fall down below 25 mV by the internal SS pull-down switch. The SS pin can be pulled down by an external switch to stop switching, but pulling up to enable switching is not recommended. The startup delay (see Figure 24) should be long enough for the high-side boot capacitor to be fully charged by the internal BST charge pump. This defines the recommended minimum C_SS value, which is especially important when V_VIN is greater than 9 V.

Equation 12.

Also, the value of C_SS should be large enough to charge the output capacitor during soft-start time.

Equation 13.

7.3.9 HO and LO Drivers

The LM5121 contains two strong N-channel MOSFET gate drivers and a high-side level shifter to drive the external N-channel MOSFET switches. The high-side gate driver works in conjunction with an external bootstrap diode D_BST, and bootstrap capacitor C_BST. During the on-time of the low-side N-channel MOSFET driver, the SW pin voltage is approximately 0 V and the C_BST is charged from VCC through the D_BST. A 0.1–μF or larger ceramic capacitor, connected with short traces between the BST and SW pin, is recommended.

The LO and HO outputs are controlled with an adaptive dead-time methodology which ensures that both outputs are never enabled at the same time. When the controller commands LO to be enabled, the adaptive dead-time logic first disables HO and waits for HO-SW voltage to drop. LO is then enabled after a small delay (HO Fall to LO Rise Delay). Similarly, the HO turn-on is delayed until the LO voltage has discharged. HO is then enabled after a small delay (LO Fall to HO Rise Delay). This technique ensures adequate dead-time for any size N-channel MOSFET or parallel MOSFET configurations especially when VCC is supplied by a higher external voltage source. Use caution when adding series gate resistors, as this may decrease the effective dead-time.

Care should be exercised in selecting the N-channel MOSFET devices threshold voltage when the VIN voltage range is below the VCC regulation level or a bypass operation is required. If bypass operation is required when output voltage is less than 12 V, a logic level device should be selected for the high-side N-channel MOSFET. During startup at low input voltages, the low-side N-channel MOSFET's gate plateau voltage should be sufficiently low to completely enhance the N-channel MOSFET device. If the low-side MOSFET drive voltage is lower than the low-side MOSFET gate plateau voltage during startup, the regulator may not start properly and it may operate at the maximum duty cycle in a high power dissipation state. This condition can be avoided by selecting a lower threshold N-channel MOSFET or by increasing V_IN(STARTUP) with the UVLO pin programming.

7.3.10 Bypass Operation (V_OUT = V_IN)

The LM5121 allows 100% duty cycle operation for the high-side synchronous switch when the input supply voltage is equal to or greater than the target output voltage. An internal 200 μA BST charge pump maintains sufficient high-side driver supply voltage to keep the high-side N-channel MOSFET switch on without the power stage switching. The internal BST charge pump is enabled when the UVLO pin voltage is greater than 1.2 V, the VCC voltage exceeds the VCC UV threshold and DG to DS voltage is greater than the V_GS detection threshold. The BST charge pump generates 5.3 V minimum BST to SW voltage when SW voltage is greater than 9 V. This requires minimum 9 V boost output voltage for proper bypass operation. The leakage current of the boot diode should be always less than the BST charge pump sourcing current to maintain a sufficient driver supply voltage at both low and high temperatures. Forced PWM mode is the recommended PWM configuration when bypass operation is required.

7.3.11 Cycle-by-Cycle Current Limit

The LM5121 features a peak cycle-by-cycle current limit function. If the CSP to CSN voltage exceeds the 75–mV cycle-by-cycle current limit threshold, the current limit comparator immediately terminates the LO output.

For the case where the inductor current overshoots the desired limit, such as inductor saturation, the current limit comparator blocks LO pulses until the current has decayed below the current limit threshold. Peak inductor current in current limit can be calculated as follows:

Equation 14.

7.3.12 Circuit Breaker Function

In addition to the hiccup mode short circuit / overload protection, LM5121 provides a circuit breaker function for maximum safety. If the input current increases rapidly due to a fault, the current through the disconnection switch may exceed the inrush control threshold before the inrush control loop is able to respond. If the sensed current exceeds the circuit breaker threshold, the disconnection switch is quickly turned off through an internal switch at the DG pin until current sense input falls below the circuit breaker disable threshold. If the RES pin voltage is less than 1.2 V, the controller then restarts the inrush control procedure.

7.3.13 Clock Synchronization

The SYNCIN/RT pin can be used to synchronize the internal oscillator to an external clock. The positive going synchronization clock at the RT pin must exceed the RT sync rising threshold and the negative going synchronization clock at RT pin must exceed the RT sync falling threshold to trip the internal synchronization pulse detector.

With the configuration in Figure 25, the frequency of the external synchronization pulse is recommended to be within +/–20% of the internal oscillator frequency programmed by RT resistor. The actual operating range is ±100/40% of the programmed frequency. For example, 900 kHz external synchronization clock and 20 kΩ RT resistor are required for 450 kHz switching. The internal oscillator can be synchronized by AC coupling a positive edge into the RT pin. A 5-V amplitude pulse signal coupled through 100-pF capacitor is a good starting point. The RT resistor is always required in this configuration, whether the oscillator is free running or externally synchronized.

Care should be taken to guarantee that the RT pin voltage does not go below –0.3 V at the falling edge of the external pulse. This may limit the duty cycle of external synchronization pulse. There is approximately 400 ns delay from the rising edge of the external pulse to the rising edge of LO.

Figure 25. Oscillator Synchronization Through AC Coupling

With the configuration in Figure 26, the internal oscillator can be synchronized by connecting the external synchronization clock to the RT pin through the RT resistor with free of the duty cycle limit. The output stage of the external clock source should be a low impedance totem-pole structure and the default logic state of f_SYNC should be low.

Figure 26. Oscillator Synchronization Through a Resistor

7.3.14 Maximum Duty Cycle

When operating with a high PWM duty cycle, the low-side N-channel MOSFET device is forced off each cycle. This forced LO off-time limits the maximum duty cycle of the controller. When designing a boost regulator with high switching frequency and high duty cycle requirements, check the required maximum duty cycle. The minimum input supply voltage which can achieve the target output voltage is estimated from Equation 15 .

Equation 15.

100 ns of margin is recommended.

7.3.15 Thermal Protection

Internal thermal shutdown circuitry is provided to protect the controller in the event the maximum junction temperature is exceeded. When activated, typically at 165°C, the controller is forced into a low-power shutdown mode, disabling the output drivers, disconnection switch and the VCC regulator. This feature is designed to prevent overheating and destroying the device.

7.4.1 Hiccup Mode Short Circuit and Overload Protection

If cycle-by-cycle current limit or inrush current limit is reached during any cycle, a 30-μA RES current is sourced into the RES capacitor for the remainder of the clock cycle. If the RES capacitor voltage exceeds the 1.2-V restart threshold, a hiccup mode protection sequence is initiated. In the hiccup mode, the DG pin is discharged to GND if the inrush current limit is reached, the SS capacitor is discharged to GND, both LO and HO outputs are disabled, and the voltage on the RES capacitor is ramped up and down between 2-V and 4-V eight times.

After the eighth RES pin cycle, the DG pin is released and charged by the DG charge pump. If a 2~3-V zener diode is connected in parallel with the RES capacitor, the regulator enters into the hiccup mode and never restarts until UVLO shutdown is cycled. Connect the RES pin directly to the AGND when the hiccup mode operation is not required.

Figure 27. Hiccup Mode Short Circuit Protection
(Start-Up With Output Short)

Figure 28. Hiccup Mode Overload Protection (Overload After Start-Up)

7.4.2 MODE Control (Forced PWM Mode and Diode Emulation Mode)

A fully synchronous boost regulator implemented with a high-side MOSFET rather than a diode has the capability to sink current from the output in conditions such as light load, overvoltage or load transient. The LM5121 can be configured to operate in either forced PWM mode or diode emulation mode.

In forced PWM mode (FPWM), reverse current flow in high-side N-channel MOSFET switch is allowed and the inductor current conducts continuously at light or no load conditions. The benefit of the forced PWM mode is fast light load to heavy load transient response and constant frequency operation at light or no load conditions. To enable forced PWM mode, connect the MODE pin to VCC or tie it to a voltage greater than 1.2 V. In the FPWM mode, reverse current flow is not limited.

In the diode emulation mode, current flow in the high-side switch is only permitted in one direction (source to drain). Turn-on of the high-side switch is allowed if the CSP to CSN voltage is greater than the 7 mV rising threshold of the zero current detection circuit during low-side switch on-time. If the CSP to CSN voltage is less than 6 mV falling threshold of the zero current detection during high-side switch on-time, reverse current flow from output to input through the high-side N-channel MOSFET is prevented and discontinuous conduction mode of operation is enabled by latching off the high-side N-channel MOSFET switch for the remainder of the PWM cycle. A benefit of the diode emulation is lower power loss at light load conditions.

Figure 29. MODE Selection

During startup the LM5121 forces diode emulation, to support startup into a pre-biased load, until the SS pin voltage exceeds 1.2 V. Forced diode emulation is terminated by a pulse from PWM comparator when SS is greater than 1.2 V. If there are no LO pulses during the soft-start period, a 350 ns one-shot LO pulse is forced at the end of soft-start to help charge the bootstrap capacitor. Due to the internal current sense delay, configuring the LM5121 for diode emulation mode should be carefully evaluated if the inductor current ripple ratio is high and the controller is operated at very high switching frequency. The transient performance during full load to no load in FPWM mode should also be verified.

7.4.3 MODE Control (Skip Cycle Mode and Pulse Skipping Mode)

Light load efficiency of the regulator typically drops as the losses associated with switching and bias currents of the converter become a significant percentage of the total power delivered to the load. In order to increase the light load efficiency the LM5121 provides two types of light load operation in diode emulation mode.

The skip cycle mode integrated into the LM5121 controller reduces switching losses and improves efficiency in light load conditions by reducing the average switching frequency. Skip cycle operation is achieved by the skip cycle comparator. When a light load condition occurs, the COMP pin voltage naturally decreases, reducing the peak current delivered by the regulator. During COMP voltage falling, the skip cycle threshold is defined as V_MODE –20 mV and during COMP voltage rising, it is defined as V_MODE +20 mV. There is 40mV of internal hysteresis in the skip cycle comparator.

When the voltage at PWM comparator input falls below V_MODE –20 mV, both HO and LO outputs are disabled. The controller continues to skip switching cycles until the voltage at PWM comparator input increases to V_MODE +20 mV, demanding more inductor current. The number of cycles skipped depends upon the load and the response time of the frequency compensation network. The internal hysteresis of skip cycle comparator helps to produce a long skip cycle interval followed by a short burst of pulses. An internal 700 kΩ pull-up and 100 kΩ pull-down resistor sets the MODE pin to 0.15 V as a default. Since the peak current limit threshold is set to 750 mV, the default skip threshold corresponds to approximately 17% of the peak level. In practice the skip level will be lower due to the added slope compensation. By adding an external pull-up resistor from MODE to the SLOPE or VCC pin or adding an external pull-down resistor to the ground, the skip cycle threshold can be programmed. Because the skip cycle comparator monitors the PWM comparator input which tracks the COMP voltage, skip cycle operation is not recommended when the bypass operation is required.

Pulse skipping operation can be achieved by connecting the MODE pin to ground. The negative 20 mV offset at the positive input of skip cycle comparator ensures the skip cycle comparator will not be triggered in normal operation. At light or no load conditions, the LM5121 skips LO pulses if the pulse width required by the regulator is less than the minimum LO on-time of the device. Pulse skipping appears as a random behavior as the error amplifier attempts to find the proper pulse width to maintain regulation at light or no load conditions.