Table 1. Bill of Materials

8.2.2.1 Setting Output Voltage

The output voltage is programmed using a resistor divider between V_OUT and GND as shown in Figure 11. The feedback resistors can be calculated as follows:

Equation 3.

where

• Vfb is 0.8 V typically

The feedback resistor ratio, α = (R1+R2) / R2, will also be used below to calculate output ripple and operating frequency.

Figure 11. Hysteretic Window

8.2.2.2 Setting Operating Frequency and Output Ripple

Although hysteretic control is a simple control scheme, the operating frequency and other performance characteristics depend on external conditions and components. If the inductance, output capacitance, ESR, V_IN, or C_ff is changed, there will be a change in the operating frequency and possibly output ripple. Therefore, care must be taken to select components which will provide the desired operating range. The best approach is to determine what operating frequency is desirable in the application and then begin with the selection of the inductor and output capacitor ESR. The design process usually involves a few iterations to select appropriate standard values that will result in the desired frequency and ripple.

Without the feedforward capacitor (C_ff), the operating frequency (F) can be approximately calculated using the formula:

Equation 4.

where

• Delay is the sum of the LM3475 propagation delay time and the PFET delay time
• The propagation delay is 90ns typically

Minimum output ripple voltage can be determined using the following equation:

8.2.2.3 Using a Feed-forward Capacitor

The operating frequency and output ripple voltage can also be significantly influenced using a speed up capacitor, C_ff, as shown in Figure 11. C_ff is connected in parallel with the high side feedback resistor, R1. The output ripple causes a current to be sourced or sunk through this capacitor. This current is essentially a square wave. Since the input to the feedback pin (FB) is a high impedance node, the bulk of the current flows through R2. This superimposes a square wave ripple voltage on the FB node. The end result is a reduction in output ripple and an increase in operating frequency. When adding C_ff, calculate the formula above with α= 1. The value of C_ff depends on the desired operating frequency and the value of R2. A good starting point is 1nF ceramic at 100kHz decreasing linearly with increased operating frequency. Also note that as the output voltage is programmed below 1.6V, the effect of C_ff will decrease significantly.

8.2.2.4 Inductor Selection

The most important parameters for the inductor are the inductance and the current rating. The LM3475 operates over a wide frequency range and can use a wide range of inductance values. Minimum inductance can be calculated using the following equation:

Equation 6.

where

• D is the duty cycle, defined as V_OUT/V_IN
• ΔI is the allowable inductor ripple current

Maximum allowable inductor ripple current should be calculated as a function of output current (I_OUT) as shown below:

ΔI_max = I_OUT x 0.3

The inductor must also be rated to handle the peak current (I_PK) and RMS current given by:

Equation 8.

The inductance value and the resulting ripple is one of the key parameters controlling operating frequency.

8.2.2.5 Output Capacitor Selection

Once the desired operating frequency and inductance value are selected, ESR must be selected based on Equation 4. This process may involve a few iterations to select standard ESR and inductance values.

In general, the ESR of the output capacitor and the inductor ripple current create the output ripple of the regulator. However, the comparator hysteresis sets the first order value of this ripple. Therefore, as ESR and ripple current vary, operating frequency must also vary to keep the output ripple voltage regulated. The hysteretic control topology is well suited to using ceramic output capacitors. However, ceramic capacitors have a very low ESR, resulting in a 90° phase shift of the output voltage ripple. This results in low operating frequency and increased output ripple. To fix this problem a low value resistor could be added in series with the ceramic output capacitor. Although counter intuitive, this combination of a ceramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. Another method is to add an external ramp at the FB pin as shown in Figure 12. By proper selection of R1 and C2, the FB pin sees faster voltage change than the output ripple can cause. As a result, the switching frequency is higher while the output ripple becomes lower. The switching frequency is approximately:

Equation 9.

Other types of capacitor, such as Sanyo POSCAP, OS-CON, and Nichicon ’NA’ series are also recommended and may be used without additional series resistance. For all practical purposes, any type of output capacitor may be used with proper circuit verification.

Capacitors with high ESL (equivalent series inductance) values should not be used. As shown in Figure 9, the output ripple voltage contains a small step at both the high and low peaks. This step is caused by and is directly proportional to the output capacitor’s ESL. A large ESL, such as in an electrolytic capacitor, can create a step large enough to cause abnormal switching behavior.

8.2.2.6 Input Capacitor Selection

A bypass capacitor is required between V_IN and ground. It must be placed near the source of the external PFET. The input capacitor prevents large voltage transients at the input and provides the instantaneous current when the PFET turns on. The important parameters for the input capacitor are the voltage rating and the RMS current rating. Follow the manufacturer’s recommended voltage de-rating. RMS current and power dissipation (PD) can be calculated with the equations below:

Equation 10.

8.2.2.7 Diode Selection

The catch diode provides the current path to the load during the PFET off time. Therefore, the current rating of the diode must be higher than the average current through the diode, which be calculated as shown:

The peak voltage across the catch diode is approximately equal to the input voltage. Therefore, the diode’s peak reverse voltage rating should be greater than 1.3 times the input voltage.

A Schottky diode is recommended, since a low forward voltage drop will improve efficiency.

For high temperature applications, diode leakage current may become significant and require a higher reverse voltage rating to achieve acceptable performance.

8.2.2.8 P-Channel MOSFET Selection

The PFET switch should be selected based on the maximum Drain-Source voltage (VDS), Drain current rating (I_D), maximum Gate-Source voltage (VGS), on resistance (R_DSON), and Gate capacitance. The voltage across the PFET when it is turned off is equal to the sum of the input voltage and the diode forward voltage. The VDS must be selected to provide some margin beyond the sum of the input voltage and Vd.

Since the current flowing through the PFET is equal to the current through the inductor, I_D must be rated higher than the maximum I_PK. During switching, PGATE swings the PFET’s gate from V_IN to ground. Therefore, A PFET must be selected with a maximum VGS larger than V_IN. To insure that the PFET turns on completely and quickly, refer to the PGATE section.

The power loss in the PFET consists of switching losses and conducting losses. Although switching losses are difficult to precisely calculate, the equation below can be used to estimate total power dissipation. Increasing R_DSON will increase power losses and degrade efficiency. Note that switching losses will also increase with lower gate threshold voltages.

Note that the R_DSON has a positive temperature coefficient. At 100°C, the R_DSON may be as much as 150% higher than the value at 25°C.

The Gate capacitance of the PFET has a direct impact on both PFET transition time and the power dissipation in the LM3475. Most of the power dissipated in the LM3475 is used to drive the PFET switch. This power can be calculated as follows:

The amount of average gate driver current required during switching (I_G) is:

And the total power dissipated in the device is:

As gate capacitance increases, operating frequency may need to be reduced, or additional heat sinking may be required to lower the power dissipation in the device.

In general, keeping the gate capacitance below 2000 pF is recommended to keep transition times (switching losses), and power losses low.

8.2.2.9 Reducing Switching Noise

Although the LM3475 employs internal noise suppression circuitry, external noise may continue to be excessive. There are several methods available to reduce noise and EMI.

MOSFETs are very fast switching devices. The fast increase in PFET current coupled with parasitic trace inductance can create unwanted noise spikes at both the switch node and at V_IN. Switching noise will increase with load current and input voltage. This noise can also propagate through the ground plane, sometimes causing unpredictable device performance. Slowing the rise and fall times of the PFET can be very effective in reducing this noise. Referring to Figure 13, the PFET can be slowed down by placing a small (1-Ω to 10-Ω) resistor in series with PGATE. However, this resistor will increase the switching losses in the PFET and will lower efficiency. Therefore it should be kept as small as possible and only used when necessary. Another method to reduce switching noise (other than good PCB layout, see Layout) is to use a small RC filter or snubber. The snubber should be placed in parallel with the catch diode, connected close to the drain of the PFET, as shown in Figure 13. Again, the snubber should be kept as small as possible to limit its impact on system efficiency. A typical range is a 10-Ω to 100-Ω resistor and a 470-pF to 2.2-nF ceramic capacitor.

Figure 13. PGATE Resistor and Snubber