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ZHCS557J February 2010 – December 2015 LM25066

PRODUCTION DATA.

封裝選項(xiàng)

機(jī)械數(shù)據(jù) (封裝 | 引腳)

NHZ|24
- MPQS005

散熱焊盤(pán)機(jī)械數(shù)據(jù) (封裝 | 引腳)

訂購(gòu)信息

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VIN, SENSE to GND⁽²⁾	–0.3	24	V
	GATE, FB, UVLO/EN, OVLO, PGD to GND⁽²⁾	–0.3	20	V
	OUT to GND	–1	20	V
	SCL, SDA, SMBA, CL, CB, ADR0, ADR1, ADR2, VDD, VAUX, DIODE, RETRY to GND	–0.3	6	V
	VIN to SENSE	–0.3	0.3	V
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The GATE pin voltage is typically 7.5 V above VIN when the LM25066 is enabled. Therefore, the Absolute Maximum Rating of 24 V for VIN and SENSE apply only when the LM25066 is disabled or for a momentary surge to that voltage since the Absolute Maximum Rating for the GATE pin is 20 V.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	MAX	UNIT
VIN, SENSE, OUT voltage	2.9	17	V
VDD	2.9	5.5	V
Junction temperature, T_J	–40	125	°C

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM25066	UNIT
		NHZ (WQFN)
		24 PINS
R_θJA	Junction-to-ambient thermal resistance	34.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28.9	°C/W
R_θJB	Junction-to-board thermal resistance	13.4	°C/W
ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
ψ_JB	Junction-to-board characterization parameter	13.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.6	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Limits in standard type are for T_J = 25°C only; limits in boldface type apply over the junction temperature (T_J) range of –40°C to 85°C unless otherwise stated. Minimum and Maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at T_J = 25°C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 12 V (see ⁽¹⁾ and ⁽³⁾).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT (VIN PIN)
I_IN-EN	Input current, enabled	UVLO = 2 V and OVLO = 0.7 V		5.8	8	mA
POR	Power on reset threshold at VIN	VIN increasing		2.6	2.8	V
POR_HYS	POR_EN hysteresis	VIN decreasing		150		mV
VDD REGULATOR (VDD PIN)
V_DD		I_VDD = 5 mA, VIN = 12 V	4.3	4.5	4.7	V
V_DD		I_VDD = 5 mA, VIN = 4.5 V	3.5	3.9	4.3	V
V_DDILIM	VDD current limit		25	45		mA
UVLO/EN, OVLO PINS
UVLO_TH	UVLO threshold	V_UVLO Falling	1.147	1.16	1.173	V
UVLO_HYS	UVLO hysteresis current	UVLO = 1 V	18	23	28	µA
UVLO_DEL	UVLO delay	Delay to GATE high		8		µs
UVLO_DEL	UVLO delay	Delay to GATE low		20		µs
UVLO_BIAS	UVLO bias current	UVLO = 3 V			1	µA
OVLO_TH	OVLO threshold	V_OVLO rising	1.141	1.16	1.185	V
OVLO_HYS	OVLO hysteresis current	OVLO = 1 V	–28	–23	–18	µA
OVLO_DEL	OVLO delay	Delay to GATE high		19		µs
OVLO_DEL	OVLO delay	Delay to GATE low		9		µs
OVLO_BIAS	OVLO bias current	OVLO = 1 V			1	µA
POWER GOOD (PGD PIN)
PGD_VOL	Output low voltage	I_SINK = 2 mA		25	60	mV
PGD_IOH	Off leakage current	V_PGD= 17 V			1	µA
PGD_DELAY	Power Good delay	V_FB to V_PG		115		ns
FB PIN
FB_TH	FB threshold	V_FB rising	1.141	1.167	1.19	V
FB_HYS	FB hysteresis current		–31	–24	–18	µA
FB_LEAK	Off leakage current	V_FB = 1 V			1	µA
POWER LIMIT (PWR PIN)
PWR_LIM	Power limit sense voltage (VIN-SENSE)	SENSE-OUT = 12 V, R_PWR = 25 kΩ	9	12.5	15	mV
I_PWR	PWR pin current	V_PWR = 2.5 V		–10		µA
R_SAT(PWR)	PWR pin impedance when disabled	UVLO = 0.7 V		180		Ω
GATE CONTROL (GATE PIN)
I_GATE	Source current	Normal operation	–28	–22	–16	µA
	Fault sink current	UVLO = 1 V	1.5	2	2.5	mA
	POR circuit breaker sink current	VIN - SENSE = 150 mV or VIN < R_POR, V_GATE = 5 V	105	190	275	mA
V_GATE	Gate output voltage in normal operation	GATE voltage with respect to ground	17	18.8	20.3	V
OUT PIN
I_OUT-EN	OUT bias current, enabled	OUT = VIN, normal operation		16		µA
I_OUT-DIS	OUT bias current, disabled⁽²⁾	Disabled, OUT = 0 V, SENSE = VIN		–12		µA
CURRENT LIMIT
V_CL	Threshold voltage	CL = GND	22.5	25	27	mV
		CL = GND, T_J = 10°C to 85°C	23	25	27
		CL = VDD	42.3	46	49.7
I_SENSE	SENSE input current	Enabled, SENSE = OUT		33		µA
		Disabled, OUT = 0 V		46
		Enabled, OUT = 0 V		45
CIRCUIT BREAKER
V_CB	Threshold voltage × 1.8	VIN - SENSE, CL = GND, CB = GND	35	45	55	mV
V_CB	CB:CL ratio	CB = GND	1.6	1.8	2
V_CB	Threshold voltage × 3.6	VIN - SENSE, CL = GND, CB = VDD	70	90	110	mV
V_CB	CB:CL ratio	CB = VDD	3.1	3.6	4
TIMER (TIMER PIN)
V_TMRH	Upper threshold		1.54	1.7	1.85	V
V_TMRL	Lower threshold	Restart cycles	0.85	1.0	1.07	V
		End of 8^th cycle		0.3		V
		Re-enable threshold		0.3		V
I_TIMER	Insertion time current	TIMER pin = 2 V	–3	–5.5	–8	µA
	Sink current, end of insertion time		1.4	1.9	2.4	mA
	Fault detection current		–120	–90	–60	µA
	Fault sink current			2.8		µA
DC_FAULT	Fault restart duty cycle			0.67%
INTERNAL REFERENCE
V_REF	Reference voltage		2.703	2.73	2.757	V
ADC AND MUX
	Resolution			12		Bits
INL	Integral non-linearity	ADC only		±1		LSB
TELEMETRY ACCURACY
IIN_FSR	Current input full scale range	CL = GND		30.2		mV
IIN_FSR	Current input full scale range	CL = VDD		60.4		mV
IIN_LSB	Current input LSB	CL = GND		7.32		µV
IIN_LSB	Current input LSB	CL = VDD		14.64		µV
VAUX_FSR	VAUX input full scale range			1.16		V
VAUX_LSB	VAUX input LSB			283.2		µV
VIN_FSR	Input voltage full scale range			18.7		V
VIN_LSB	Input voltage LSB			4.54		mV
IIN_ACC	Input current accuracy	VIN – SENSE = 25 mV, CL = GND	–2.7		2.4
IIN_ACC	Input current accuracy	VIN – SENSE = 25 mV, CL = GND T_J = 10°C to 85°C	–2.4%		2.4%
V_ACC	VAUX, VIN, VOUT accuracy	VIN, VOUT = 12 V VAUX = 1 V	–1.6%		1.4%
V_ACC	VAUX, VIN, VOUT accuracy	VIN, VOUT = 12 V VAUX = 1 V T_J = 10°C to 85°C	–1.4%		1.4%
PIN_ACC	Input power accuracy	VIN = 12 V, VIN – SENSE = 25 mV, CL = GND	–3%		3%
REMOTE DIODE TEMPERATURE SENSOR
T_ACC	Temperature accuracy using local diode	T_A = 10°C to 85°C		2	10	°C
T_ACC	Remote diode resolution			9		bits
I_DIODE	External diode current source	High level		250	300	µA
I_DIODE	External diode current source	Low level		9.4		µA
	Diode current ratio			26
PMBUS PIN THRESHOLDS (SMBA, SDA, SCL)
V_IL	Data, clock input low voltage				0.8	V
V_IH	Data, clock input high voltage		2.1		5.5	V
V_OL	Data output low voltage	I_PULLUP = 500 µA	0		0.4	V
I_LEAK	Input leakage current	SDA, SMBA, SCL = 5 V			1	µA
CONFIGURATION PIN THRESHOLDS (CB, CL, RETRY)
V_IH	Threshold voltage		3			V
I_LEAK	Input leakage current	CL, CB, RETRY = 5 V			1	mA

(1) Current out of a pin is indicated as a negative value.

(2) OUT bias current (disabled) due to leakage current through an internal 0.9 MΩ resistance from SENSE to VOUT.

(3) All limits are specified. All electrical characteristics having room temperature limits are tested during production at T_A = 25°C. All hot and cold limits are specified by correlating the electrical characteristics to process and temperature variations and applying statistical process control.

7.6 Timing Requirements

		MIN	MAX	UNIT
F_SMB	SMBus operating frequency	10	400	kHz
t_BUF	Bus free time between stop and start condition	1.3		µs
t_HD:STA	Hold time after (repeated) start condition. After this period, the first clock is generated.	0.6		µs
t_SU:STA	Repeated start condition setup time	0.6		µs
t_SU:STO	Stop condition setup time	0.6		µs
t_HD:DAT	Data hold time	300		ns
t_SU:DAT	Data setup time	100		ns
t_TIMEOUT	Clock low time-out⁽¹⁾	25	35	ms
t_LOW	Clock low period	1.5		µs
t_HIGH	Clock high period⁽²⁾	0.6		µs
t_LOW:SEXT	Cumulative clock low extend time (slave device)⁽³⁾		25	ms
t_LOW:MEXT	Cumulative low extend time (master device)⁽⁴⁾		10	ms
t_F	Clock or data fall time⁽⁵⁾	20	300	ns
t_R	Clock or data rise time⁽⁵⁾	20	300	ns

(1) Devices participating in a transfer will timeout when any clock low exceeds the value of T_TIMEOUT,MIN of 25 ms. Devices that have detected a timeout condition must reset the communication no later than T_TIMEOUT,MAX of 35 ms. The maximum value must be adhered to by both a master and a slave as it incorporates the cumulative stretch limit for both a master (10 ms) and a slave (25 ms).

(2) T_{HIGH MAX} provides a simple method for devices to detect bus idle conditions.

(3) T_LOW:SEXT is the cumulative time a slave device is allowed to extend the clock cycles in one message from the initial start to the stop. If a slave exceeds this time, it is expected to release both its clock and data lines and reset itself.

(4) T_LOW:MEXT is the cumulative time a master device is allowed to extend its clock cycles within each byte of a message as defined from start-to-ack, ack-to-ack, or ack-to-stop.

(5) Rise and fall time are defined with T_R = ( V_ILMAX – 0.15) to (V_IHMIN + 0.15) and T_F = 0.9 VDD to (V_ILMAX – 0.15).

7.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
CURRENT LIMIT
t_CL	Response time	VIN-SENSE stepped from 0 mV to 80 mV	1.2		µs
CIRCUIT BREAKER
t_CB	Response time	VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load	0.6	1.2	µs
TIMER (TIMER PIN)
t_{FAULT_DELAY}	Fault to GATE low delay	TIMER pin reaches the upper threshold	17		µs
ADC AND MUX
t_AQUIRE	Acquisition + conversion time	Any channel	100		µs
t_RR	Acquisition round robin time	Cycle all channels	1		ms