Table 44. Design Parameters

9.2.1.2.1 Select R_SNS and CL Setting

LM25066 can be used with a VCL of 25 mV or 46 mV. In general using the 25-mV threshold will result in a lower RSNS and lower I²R losses. This option is selected for this design by connecting the CL pin directly to VDD. It is recommended to target a current limit that is at least 10% above the maximum load current to account for the tolerance of the LM25066 current limit. Targeting a current limit of 50 A the sense resistor can be calculated using Equation 5:

Equation 5.

Typically sense resistors are only available in discrete values. If a precise current limit is desired, a sense resistor along with a resistor divider can be used as shown in Figure 39.

Figure 39. SENSE Resistor Divider

If using a resistor divider, then the next larger available sense resistor should be chosen (1 mΩ for example). The ratio of R1 and R2 can then be calculated using Equation 6:

Equation 6.

Note that the SENSE pin will pull 25 μA of current, which will create an offset across R2. It is recommended to keep R2 below 10 Ω to reduce the offset that this introduces. In addition the 1% resistors will add to the current monitoring error. Finally, if the resistor divider approach is used, the user should compute the effective sense resistance (R_SNS,EFF) using Equation 7 and use that in all equations instead of R_SNS.

Equation 7.

Note that for many applications, a precise current limit may not be required. In that case, it’s simpler to pick the next smaller available sense resistor. For this application, a 0.5-mΩ resistor can be used for a 50 A current limit.

9.2.1.2.2 Selecting the Hotswap FETs

It is critical to select the correct MOSFET for a hot swap design. The device must meet the following requirements:

• The V_DS rating should be sufficient to handle the maximum system voltage along with any ringing caused by transients. For most 12-V systems a 30-V FET is a good choice.
• The SOA of the FET should be sufficient to handle all usage cases: start-up, hot-short, start into short.
• R_DSON should be sufficiently low to maintain the junction and case temperature below the maximum rating of the FET. In fact, it is recommended to keep the steady state FET temperature below 125°C to allow margin to handle transients.
• Maximum continuous current rating should be above the maximum load current and the pulsed drain current must be greater than the current threshold of the circuit breaker. Most MOSFETs that pass the first three requirements will also pass these two.
• A V_GS rating of ± 20 V is required, because the LM25066 can pull up the gate as high as 16 V above source.
  • Otherwise, a diode (D3 in Figure 38) can be used to protect MOSFETs with a ± 12 V V_GS rating.

For this design the CSD17556Q5B was selected for its low R_DSON and good SOA. After selecting the MOSFET, the maximum steady state case temperature can be calculated using Equation 8:

Equation 8.

Note that the R_DSON is a strong function of junction temperature, which for most MOSFETs will be close to the case temperature. A few iterations of the above equations may be necessary to converge on the final R_DSON and T_C,MAX value. According to the CSD17556Q5B datasheet, its R_DSON is approximately 1.3x at 85°C. Equation 9 uses this R_DSON value to compute the T_C,MAX.

Equation 9.

This maximum steady state case temperature indicates that a second MOSFET may be needed to reduce and distribute power dissipation during normal operation. When using parallel MOSFETs, the maximum steady state case temperature can be calculated using Equation 10:

Equation 10.

Thus using two of the CSD17556Q5B in parallel will result in a steady state temperature of:

Equation 11.

Note that the computed T_C,MAX is close to the junction temperature assumed for R_DSON. Thus no further iterations are necessary.

9.2.1.2.3 Select Power Limit

In general, a lower power limit setting is preferred to reduce the stress on the MOSFET. However, when the LM25066 is set to a very low power limit setting, it has to regulate the FET current and hence the voltage across the sense resistor (V_SNS) to a very low value. V_SNS can be calculated using Equation 12:

Equation 12.

To avoid significant degradation of the power limiting a V_SNS of less than 4 mV is not recommended. Based on this requirement the minimum allowed power limit can be calculated using Equation 13:

Equation 13.

In most applications the power limit can be set to P_LIM,MIN using Equation 14. Here R_SNS and R_PWR are in Ωs and P_LIM is in Watts.

Equation 14.

So note that the minimum R_PWR would occur when V_DS = V_IN,MAX. We can then calculate the minimum R_PWR using Equation 15:

Equation 15.

The next largest available resistor should be selected. In this case a 5.23-kΩ resistor was chosen, which sets a 112.72 W power limit.

9.2.1.2.4 Set Fault Timer

The fault timer runs when the hot swap is in power limit or current limit, which is the case during start-up. Thus the timer has to be sized large enough to prevent a time-out during start-up. If the device starts directly into current limit (I_LIM) × V_DS < P_LIM) the maximum start time can be calculated using Equation 16:

Equation 16.

For most designs (including this example) I_LIM × V_DS > P_LIM so the hot swap will start in power limit and transition into current limit. In that case the estimated start time can be calculated using Equation 17:

Equation 17.

Note that the above start-time assumes constant, typical current limit and power limit values. The actual start-up time will be slightly longer, as the power limit is a function of V_DS and will decrease as the output voltage increases. To ensure that the timer never times out during start-up, it is recommended to set the fault time (t_flt) to be 2 × t_start or 10.06 ms. This will account for the variation in power limit, timer current, and timer capacitance. Thus C_TIMER can be calculated using Equation 18:

Equation 18.

The next largest available C_TIMER is chosen as 560 nF. Once the C_TIMER is chosen the actual programmed fault time can be calculated using Equation 19:

Equation 19.

9.2.1.2.5 Check MOSFET SOA

Once the power limit and fault timer are chosen, it’s critical to check that the FET will stay within its SOA during all test conditions. During a “Hot-Short” the circuit breaker will trip and the LM25066 will restart into power limit until the timer runs out. In the worst case the MOSFET’s V_DS will equal V_IN,MAX, I_DS will equal P_LIM / V_IN,MAX and the stress event will last for t_flt. For this design example the MOSFET will have 14 V, 8 A across it for 10.58 ms.

Based on the SOA of the CSD17556Q5B, it can handle 14 V, 10 A for 10 ms and it can handle 14 V, 3 A for
100 ms. The SOA for 10.58 ms can be extrapolated by approximating SOA vs time as a power function as shown in Equation 20 through Equation 23:

Equation 20.

Equation 21.

Equation 22.

Equation 23.

Note that the SOA of a MOSFET is specified at a case temperature of 25°C, while the case temperature can be much hotter during a hot-short. The SOA should be de-rated based on T_C,MAX using Equation 24:

Equation 24.

Based on this calculation the MOSFET can handle 5.24 A, 14 V for 10.58 ms at elevated case temperature, but is required to handle 8 A during a hot-short. This means the MOSFET will be at risk of getting damaged during a hot-short. In general, it is recommended for the MOSFET to be able to handle a minimum of 1.3x more power than what is required during a hot-short in order to provide margin to cover the variance of the power limit and fault time.

9.2.1.2.6 Switching to dV/dt based Start-up

For designs with large load currents and output capacitances, using a power limit based start-up can be impractical. Fundamentally, increasing load currents will reduce the sense resistor, which will increase the minimum power limit. Using a larger output capacitor will result in a longer start-up time and require a longer fault timer. Thus a longer fault timer and a larger power limit setting are required, which places more stress on the MOSFET during a hot-short or a start into short. Eventually, there will be no FETs that can support such a requirement.

To avoid this problem, a dV/dt limiting capacitor (C_dV/dt) can be used to limit the slew rate of the gate and the output voltage. The inrush current can be set arbitrarily small by reducing the slew rate of the V_OUT. In addition, the power limit is set to satisfy the minimum power limit requirement and to keep the timer from running during start-up (make P_LIM / V_IN,MAX > I_INR). Since the timer doesn’t run during start-up it can be made small to reduce the stress that the MOSFET experiences during a start into short or a hot-short.

The D2 prevents the charge of C_dV/dt from interfering with the power limit loop during a hot-short event and Q3 discharges C_dV/dt when the hot swap gate comes down.

9.2.1.2.7 Choosing the VOUT Slew Rate

The inrush current should be kept low enough to keep the MOSFET within its SOA during start-up. Note that the total energy dissipated in the MOSFET during start-up is constant regardless of the inrush time. Thus, stretching it out over a longer time will always reduce the stress on the MOSFET as long as the load is off during start-up.

When choosing a target slew rate, one should pick a reasonable number, check the SOA and reduce the slew rate if necessary. Using 0.25 V/ms as a starting point the inrush current can be computed as follows:

Equation 25.

Assuming a maximum input voltage of 14 V, it will take 56 ms to start-up. Note that the power dissipation of the FET will start at V_IN,MAX × I_INR and reduce to zero as the V_DS of the MOSFET is reduced. Note that the SOA curves assume the same power dissipation for a given time. A conservative approach is to assume an equivalent power profile where P_FET = V_IN,MAX × I_INR for t = t_start-up /2. In this instance, the SOA can be checked by looking at a 14 V, 1.4 A, 28 ms pulse. Using the same technique as Check MOSFET SOA, the MOSFET SOA can be estimated with Equation 26.

Equation 26.

This value has to also be derated for temperature. For this calculation, it is assumed that T_C can equal T_A,MAX when the board is plugged in. This would occur if a board is plugged in at an elevated ambient temperature environment.

Equation 27.

Based on this calculation the MOSFET can handle 4.44 A, 14 V for 28 ms at elevated ambient temperature, and is required to handle 1.4 A. This indicates the MOSFET will stay well-within its SOA during a start-up if the slew rate is 0.25 V/ms or less. Note that if the load is off during start-up, the total energy dissipated in the FET is constant regardless of the slew rate. Thus a lower slew rate will always place less stress on the FET. To ensure that the slew rate is at most 0.25 V/ms the CdV/dt should be chosen with Equation 28.

Equation 28.

The next largest available C_dV/dt is chosen to be 100 nF. Then the typical slew rate and start time can be computed to be 0.22 V/ms as shown below, making the typical start time 55 ms, assuming 12 V input.

Equation 29.

In certain applications, T_C,MAX may be used for temperature derating instead. This would only occur if a hot board is unplugged and then plugged back in before it cools off to ambient temperature. This is worst case and for many applications, the T_A,MAX can be used for this derating.

Equation 30.

Based on this calculation using T_C,MAX for derating, the MOSFET can handle 3.15 A, 14 V for 28 ms at elevated case temperature, and is required to handle 1.4 A. This indicates the MOSFET will stay well-within its SOA during a start-up if the slew rate is 0.25 V/ms or less.

9.2.1.2.8 Select Power Limit and Fault Timer

When picking the power limit, it needs to meet 2 requirements:

1. Power limit is large enough to avoid operating with V_SNS < 4 mV
2. Power limit is large enough to ensure that the timer doesn’t run during start up. Picking a power limit such that it is 2x of I_INR,MAX × V_IN,MAX is good practice.

Thus the minimum allowed power limit can be computed with Equation 31.

Equation 31.

Next, the power limit is set to PLIM,MIN using the equation below. Here RSNS and RPWR are in Ωs and PLIM is in Watts.

Equation 32.

The closest available resistor should be selected. In this case a 5.23-kΩ resistor was chosen.

Next a fault timer value should be selected. In general, the timer value should be decreased until there is enough margin between available SOA and the power pulse the FET experiences during a hot-short. For this design a 22-nF CTIMER was chosen corresponding to a 420-µs fault time. The available SOA is extrapolated using the method described earlier.

Equation 33.

Equation 34.

Equation 35.

Equation 36.

Next the available SOA is derated for temperature:

Equation 37.

Note that only 4 A was required, while the FET can support 17.17A. This confirms that the design will be robust and have plenty of margin.

9.2.1.2.9 Set Undervoltage and Overvoltage Threshold

By programming the UVLO and OVLO thresholds the LM25066 enables the series pass device (Q₁) when the input supply voltage (V_SYS) is within the desired operational range. If V_SYS is below the UVLO threshold, or above the OVLO threshold, Q₁ is switched off, denying power to the load. Hysteresis is provided for each threshold.

9.2.1.2.9.1 Option A

The configuration shown in Figure 40 requires three resistors (R1-R3) to set the thresholds.

Figure 40. UVLO and OVLO Thresholds Set By R1-R3

The procedure to calculate the resistor values is as follows:

• Choose the upper UVLO threshold (V_UVH), and the lower UVLO threshold (V_UVL).
• Choose the upper OVLO threshold (V_OVH).
• The lower OVLO threshold (V_OVL) cannot be chosen in advance in this case, but is determined after the values for R1-R3 are determined. If V_OVL must be accurately defined in addition to the other three thresholds, see Option B below. The resistors are calculated as follows:
Equation 38.
Equation 39.
Equation 40.

The lower OVLO threshold is calculated from:

Equation 41.

As an example, assume the application requires the following thresholds: V_UVH = 8 V, V_UVL = 7 V, V_OVH = 15 V.

Equation 42.
Equation 43.
Equation 44.

The lower OVLO threshold calculates to 12.03 V and the OVLO hysteresis is 2.97 V. Note that the OVLO hysteresis is always slightly greater than the UVLO hysteresis in this configuration. When the R1-R3 resistor values are known, the threshold voltages and hysteresis are calculated from the following:

Equation 45.
Equation 46.
Equation 47. V_UV(HYS) = R1 × 23µA
Equation 48.
Equation 49.
Equation 50. V_OV(HYS) = (R1 + R2) × 23µA

9.2.1.2.9.2 Option B

If all four thresholds must be accurately defined, the configuration in Figure 41 can be used.

Figure 41. Programming the Four Thresholds

The four resistor values are calculated as follows:

• Choose the upper and lower UVLO thresholds (V_UVH) and (V_UVL).
Equation 51.
Equation 52.
• Choose the upper and lower OVLO threshold (V_OVH) and (V_OVL).
Equation 53.
Equation 54.

As an example, assume the application requires the following thresholds: V_UVH = 8 V, V_UVL = 7 V, V_OVH = 15.5 V, and V_OVL = 14 V. Therefore V_UV(HYS) = 1 V and V_OV(HYS) = 1.5 V. The resistor values are:

Equation 55. R1 = 43.5 kΩ, R2 = 8.64 kΩ

Equation 56. R3 = 65.2 kΩ, R4 = 5.27 kΩ

When the R1-R4 resistor values are known, the threshold voltages and hysteresis are calculated from the following:

Equation 57.

Equation 58.

Equation 59. V_UV(HYS) = R1 × 23 µA

Equation 60.

Equation 61.

Equation 62. V_OV(HYS) = R3 × 23 µA

9.2.1.2.9.3 Option C

The minimum UVLO level is obtained by connecting the UVLO/EN pin to VIN as shown in Figure 42. Q₁ is switched on when the VIN voltage reaches the POR threshold (? 2.6 V). The OVLO thresholds are set using R3, R4. Their values are calculated using the procedure in Option B.

Figure 42. UVLO = POR

For this design example option B is used and the following values are targeted: VUVH = 10 V, VUVL = 9 V, VOVH = 15 V, VOVL = 14 V. R1, R2, R3, and R4 are computed using the equations below:

Equation 63.

Equation 64.

Equation 65.

Equation 66.

Nearest available 1% resistors should be chosen. Set R1 = 43.2 kΩ, R2 = 6.49 kΩ, R3 = 43.2 kΩ, and R4 = 3.65 kΩ.

9.2.1.2.10 Power Good Pin

When the voltage at the FB pin increases above its threshold, the internal pulldown acting on the PGD pin is disabled allowing PGD to rise to V_PGD through the pullup resistor, R_PG, as shown in Figure 44. The pullup voltage (V_PGD) can be as high as 17 V, and can be higher or lower than the voltages at VIN and OUT. VDD is a convenient choice for V_PGD as it allows interface to low voltage logic and avoids glitching on PGD during power-up. If a delay is required at PGD, suggested circuits are shown in Figure 45. In Figure 45A capacitor C_PG adds delay to the rising edge, but not to the falling edge. In Figure 45B, the rising edge is delayed by R_PG1 + R_PG2 and C_PG, while the falling edge is delayed a lesser amount by R_PG2 and C_PG. Adding a diode across R_PG2 (Figure 45C) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

Setting the output threshold for the PGD pin requires two resistors (R4, R5) as shown in Figure 43. While monitoring the output voltage is shown in Figure 43, R4 can be connected to any other voltage which requires monitoring.

The resistor values are calculated as follows:

Choose the upper and lower threshold (V_PGDH) and (V_PGDL) at V_OUT.

Equation 67.

Figure 43. Programming the PGD Threshold

Figure 44. Power Good Output

Figure 45. Adding Delay to the Power Good Output Pin

For this example PGDH of 9.25 V and PGDL of 8.75 V is targeted. R5 and R6 are computed using the equations below:

Equation 68.

Equation 69.

Nearest available 1% resistors should be chosen. Set R5 = 10 kΩ and R6 = 1.5 kΩ.

9.2.1.2.11 Input and Output Protection

Proper operation of the LM25066 hot swap circuit requires a voltage clamping element present on the supply side of the connector into which the hot swap circuit is plugged in. A TVS is ideal, as depicted in Figure 46. The TVS is necessary to absorb the voltage transient generated whenever the hot swap circuit shuts off the load current. This effect is the most severe during a hot-short when a large current is suddenly interrupted when the FET shuts off. The TVS should be chosen to have minimal leakage current at V_IN,MAX and to clamp the voltage to under 24 V during hot-short events. For many high power applications, 5.0SMDJ13A is a good choice.

If the load powered by the LM25066 hot swap circuit has inductive characteristics, a Schottky diode is required across the LM25066's output, along with some load capacitance. The capacitance and the diode are necessary to limit the negative excursion at the OUT pin when the load current is shut off.

Figure 46. Output Diode Required for Inductive Loads

9.2.1.2.12 Final Schematic and Component Values

Figure 38 shows the schematic used to implement the requirements described in the previous section. In addition, Table 45 provides the final component values that were used to meet the design requirements for a
12-V, 45-A hot swap design. The application curves in the next section are based on these component values.