ZHCS349G September 2011 – January 2015 ISO7640FM , ISO7641FM
UNLESS OTHERWISE NOTED, this document contains PRODUCTION DATA.
- 1 特性
- 2 應(yīng)用
- 3 說明
- 4 修訂歷史記錄
- 5 Pin Configuration and Functions
-
6 Specifications
- 6.1 Absolute Maximum Ratings
- 6.2 ESD Ratings
- 6.3 Recommended Operating Conditions
- 6.4 Thermal Information
- 6.5 Electrical Characteristics: VCC1 and VCC2 at 5 V ±10%
- 6.6 Electrical Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
- 6.7 Electrical Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
- 6.8 Electrical Characteristics: VCC1 and VCC2 at 3.3 V ±10%
- 6.9 Electrical Characteristics: VCC1 and VCC2 at 2.7 V
- 6.10 Supply Current: VCC1 and VCC2 at 5 V ±10%
- 6.11 Supply Current: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
- 6.12 Supply Current: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
- 6.13 Supply Current: VCC1 and VCC2 at 3.3 V ±10%
- 6.14 Supply Current: VCC1 and VCC2 at 2.7 V
- 6.15 Switching Characteristics: VCC1 and VCC2 at 5 V ±10%
- 6.16 Switching Characteristics: VCC1 at 5 V ±10% and VCC2 at 3.3 V ±10%
- 6.17 Switching Characteristics: VCC1 at 3.3 V ±10% and VCC2 at 5 V ±10%
- 6.18 Switching Characteristics: VCC1 and VCC2 at 3.3 V ±10%
- 6.19 Switching Characteristics: VCC1 and VCC2 at 2.7 V
- 6.20 Typical Characteristics
- 7 Parameter Measurement Information
- 8 Detailed Description
- 9 Application and Implementation
- 10Power Supply Recommendations
- 11Layout
- 12器件和文檔支持
- 13機(jī)械封裝和可訂購信息
封裝選項(xiàng)
機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
散熱焊盤機(jī)械數(shù)據(jù) (封裝 | 引腳)
- DW|16
訂購信息
8 Detailed Description
8.1 Overview
The isolator in Figure 13 is based on a capacitive isolation barrier technique. The I/O channel of the device consists of two internal data channels, a high-frequency channel (HF) with a bandwidth from 100 kbps up to
150 Mbps, and a low-frequency channel (LF) covering the range from 100 kbps down to DC. In principle, a single- ended input signal entering the HF-channel is split into a differential signal via the inverter gate at the input. The following capacitor-resistor networks differentiate the signal into transients, which then are converted into differential pulses by two comparators. The comparator outputs drive a NOR-gate flip-flop whose output feeds an output multiplexer. A decision logic (DCL) at the driving output of the flip-flop measures the durations between signal transients. If the duration between two consecutive transients exceeds a certain time limit, (as in the case of a low-frequency signal), the DCL forces the output-multiplexer to switch from the high- to the low-frequency channel.
Because low-frequency input signals require the internal capacitors to assume prohibitively large values, these signals are pulse-width modulated (PWM) with the carrier frequency of an internal oscillator, thus creating a sufficiently high frequency signal, capable of passing the capacitive barrier. As the input is modulated, a low-pass filter (LPF) is needed to remove the high-frequency carrier from the actual data before passing it on to the output multiplexer.
8.2 Functional Block Diagram
Figure 13. Conceptual Block Diagram of a Digital Capacitive Isolator
8.3 Feature Description
| PRODUCT | RATED ISOLATION |
PACKAGE | INPUT THRESHOLD |
DATA RATE, INPUT FILTER |
CHANNEL DIRECTION |
|---|---|---|---|---|---|
| ISO7640FM | 6 KVPK / 5 KVRMS(1) |
DW-16 | 1.5 V TTL | 150 Mbps, No Noise Filter |
4 Forward, 0 Reverse |
| ISO7641FM | 3 Forward, 1 Reverse |
8.3.1 IEC Insulation and Safety-Related Specifications for DW-16 Package
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| L(I01) | Minimum air gap (Clearance) | Shortest terminal to terminal distance through air | 8.3 | mm | |||
| L(I02)(1) | Minimum external tracking (Creepage) | Shortest terminal to terminal distance across the package surface | 8.1 | mm | |||
| CTI | Tracking resistance (Comparative Tracking Index) | DIN IEC 60112 / VDE 0303 Part 1 | ≥400 | V | |||
| Minimum Internal Gap (Internal Clearance) | Distance through the insulation | 0.014 | mm | ||||
| RIO(2) | Isolation resistance, Input to Output | VIO = 500 V, TA = 25°C | >1012 | Ω | |||
| VIO = 500 V, 100°C ≤ TA ≤ TA max | >1011 | ||||||
| CIO(2) | Barrier capacitance, Input to Output | VI = 0.4 sin (2πft), f = 1MHz | 2 | pF | |||
| CI(3) | Input capacitance | VI = VCC/2 + 0.4 sin (2πft), f = 1MHz, VCC = 5 V | 2 | pF | |||
NOTE
Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit-board (PCB) do not reduce this distance.
Creepage and clearance on a PCB become equal according to the measurement techniques shown in the Isolation Glossary. Techniques such as inserting grooves and/or ribs on a PCB are used to help increase these specifications.
8.3.2 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics
over recommended operating conditions (unless otherwise noted)(1)
| PARAMETER | TEST CONDITIONS | SPECIFICATION | UNIT | |
|---|---|---|---|---|
| VIORM | Maximum working insulation voltage |
1414 | VPEAK | |
| VPR | Input-to-output test voltage | After Input/Output safety test subgroup 2/3, VPR = VIORM x 1.2, t = 10 s, Partial discharge < 5 pC |
1697 | VPEAK |
| Method a, After environmental tests subgroup 1, VPR = VIORM x 1.6, t = 10 s, Partial Discharge < 5 pC |
2262 | |||
| Method b1, 100% Production test VPR = VIORM x 1.875, t = 1 s Partial discharge < 5 pC |
2652 | |||
| VIOTM | Maximum transient overvoltage | VTEST = VIOTM
t = 60 sec (Qualification) t = 1 sec (100% Production) |
6000 | VPEAK |
| RS | Insulation resistance | VIO = 500 V at TS | >109 | Ω |
| Pollution degree | 2 | |||
Table 1. IEC 60664-1 Ratings Table
Table 2. Regulatory Information
| VDE | TUV | CSA | UL | CQC |
|---|---|---|---|---|
| Certified according to DIN V VDE V 0884-10 (VDE V 0084-10):2006-12 | Certified according to EN/UL/CSA 60950-1 and EN/UL/CSA 61010-1 | Approved under CSA Component Acceptance Notice 5A, IEC 61010-1, IEC 60950-1, IEC 60601-1 | Recognized under UL 1577 Component Recognition Program | Certified according to GB4943.1-2011 |
| Basic Insulation, Maximum Transient Overvoltage, 6000 VPK , Maximum Working Voltage, 1414 VPK | 5000 VRMS Isolation Rating, Reinforced Insulation, 400 VRMS maximum working voltage, Basic Insulation, 600 VRMS maximum working voltage | 5000 VRMS Isolation Rating, 380 VRMS Reinforced and 760 VRMS Basic working voltage per CSA 60950-1-07 and IEC 60950-1 (2nd Ed.), 300 VRMS Reinforced and 600 VRMS Basic working voltage per CSA 61010-1-04 and IEC 61010-1 (2nd Ed.), 2 Means of Patient Protection at 125 VRMS per CSA 60601-1:08 and IEC 60601-1 (3rd Ed.) |
Single Protection, 4243 VRMS(1) | Reinforced Insulation, Altitude ≤ 5000 m, Tropical Climate, 250 VRMS maximum working voltage |
| Certificate number: 40016131 | Certificate number: U8V 13 09 77311 010 | Master contract number: 220991 | File Number: E181974 | Certificate number: CQC14001109542 |
8.3.3 Safety Limiting Values
Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the IO can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
Table 3. Safety Limiting Values
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| IS | Safety input, output, or supply current | DW-16 | θJA = 72°C/W, VI = 5.5 V, TJ = 150°C, TA = 25°C | 316 | mA | ||
| θJA = 72°C/W, VI = 3.6 V, TJ = 150°C, TA = 25°C | 482 | ||||||
| θJA = 72°C/W, VI = 2.7 V, TJ = 150°C, TA = 25°C | 643 | ||||||
| TS | Maximum case temperature | 150 | °C | ||||
The safety-limiting constraint is the absolute maximum junction temperature specified in the absolute maximum ratings table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of a device installed on a High-K Test Board for Leaded Surface Mount Packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.
Figure 14. DW-16 θJC Thermal Derating Curve per DIN V VDE V 0884-10
8.4 Device Functional Modes
Table 4. Function Table(1)
| VCCI | VCCO | INPUT (INx) |
OUTPUT ENABLE (ENx) |
OUTPUT (OUTx) |
|---|---|---|---|---|
| PU | PU | H | H or Open | H |
| L | H or Open | L | ||
| X | L | Z | ||
| Open | H or Open | L | ||
| PD | PU | X | H or Open | L |
| PD | PU | X | L | Z |
| X | PD | X | X | Undetermined |