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ZHCSDJ9B January 2015 – April 2015 ISO7330C , ISO7330FC , ISO7331C , ISO7331FC

PRODUCTION DATA.

封裝選項

請參考 PDF 數據表獲取器件具體的封裝圖。

機械數據 (封裝 | 引腳)

DW|16

散熱焊盤機械數據 (封裝 | 引腳)

訂購信息

6 Specifications

6.1 Absolute Maximum Ratings⁽¹⁾

		MIN	MAX	UNIT
Supply voltage⁽²⁾	V_CC1 , V_CC2	–0.5	6	V
Voltage ⁽²⁾	INx, OUTx, ENx	–0.5	V_CC+0.5⁽³⁾	V
Output current, I_O			±15	mA
Junction temperature, T_J			150	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltage values are with respect to network ground terminal and are peak voltage values.

(3) Maximum voltage must not exceed 6 V.

6.2 ESD Ratings

			VALUE	UNIT
V_ESD	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾		±4000	V
V_ESD	Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±1500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

		MIN	TYP	MAX	UNIT
V_CC1, V_CC2	Supply voltage	3		5.5	V
I_OH	High-level output current	–4			mA
I_OL	Low-level output current			4	mA
V_IH	High-level input voltage	2		5.5	V
V_IL	Low-level input voltage	0		0.8	V
t_ui	Input pulse duration	40			ns
1 / t_ui	Signaling rate	0		25	Mbps
T_J⁽¹⁾	Junction temperature			136	°C
T_A	Ambient temperature	-40	25	125	°C

(1) To maintain the recommended operating conditions for T_J, see the Thermal Information table.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾			DW PACKAGE	UNIT
THERMAL METRIC⁽¹⁾			(16) PINS	UNIT
R_θ_JA	Junction-to-ambient thermal resistance		78.3	°C/W
R_θJCtop	Junction-to-case (top) thermal resistance		40.9
R_θJB	Junction-to-board thermal resistance		42.9
ψ_JT	Junction-to-top characterization parameter		15.3
ψ_JB	Junction-to-board characterization parameter		42.4
R_θJCbot	Junction-to-case (bottom) thermal resistance		N/A
P_D (ISO7330)	Maximum Power Dissipation by ISO7330	V_CC1 = V_CC2 = 5.5V, T_J = 150°C, C_L = 15pF, Input a 12.5 MHz 50% duty cycle square wave	70	mW
P_D1 (ISO7330)	Maximum Power Dissipation by Side-1 of ISO7330		20
P_D2 (ISO7330)	Maximum Power Dissipation by Side-2 of ISO7330		50
P_D (ISO7331)	Maximum Power Dissipation by ISO7331	V_CC1 = V_CC2 = 5.5V, T_J = 150°C, C_L = 15pF, Input a 12.5 MHz 50% duty cycle square wave	84	mW
P_D1 (ISO7331)	Maximum Power Dissipation by Side-1 of ISO7331		35
P_D2 (ISO7331)	Maximum Power Dissipation by Side-2 of ISO7331		49

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 11		V_CCO⁽¹⁾– 0.5	4.7		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 11		V_CCO⁽¹⁾ – 0.1	5		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 11			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 11			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				480		mV
I_IH	High-level input current	IN = V_CC				10	μA
I_IL	Low-level input current	IN = 0 V		–10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 14.		25	70		kV/μs
SUPPLY CURRENT (All inputs switching with square wave clock signal for dynamic I_CC measurement)
ISO7330
I_CC1	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V		0.5	1.1	mA
I_CC2		Disable	V_I = V_CC or 0 V, EN = 0 V		0.4	0.9
I_CC1		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		0.5	1.1
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		2.6	4.2
I_CC1		10 Mbps	C_L = 15pF		1.1	1.9
I_CC2		10 Mbps	C_L = 15pF		4.3	6
I_CC1		25 Mbps	C_L = 15pF		2.1	3.3
I_CC2		25 Mbps	C_L = 15pF		7	9.3
ISO7331
I_CC1	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN1 = EN2 = 0 V		0.7	1.6	mA
I_CC2		Disable	V_I = V_CC or 0 V, EN1 = EN2 = 0 V		0.7	1.3
I_CC1		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		1.8	3
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		2.4	3.6
I_CC1		10 Mbps	C_L = 15pF		2.8	4.1
I_CC2		10 Mbps	C_L = 15pF		3.8	5.1
I_CC1		25 Mbps	C_L = 15pF		4.3	6.2
I_CC2		25 Mbps	C_L = 15pF		5.8	7.8

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

6.6 Electrical Characteristics

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_OH	High-level output voltage	I_OH = –4 mA; see Figure 11		V_CCO⁽¹⁾– 0.5	3		V
V_OH	High-level output voltage	I_OH= –20 μA; see Figure 11		V_CCO⁽¹⁾– 0.1	3.3		V
V_OL	Low-level output voltage	I_OL = 4 mA; see Figure 11			0.2	0.4	V
V_OL	Low-level output voltage	I_OL = 20 μA; see Figure 11			0	0.1	V
V_I(HYS)	Input threshold voltage hysteresis				425		mV
I_IH	High-level input current	IN = V_CC				10	μA
I_IL	Low-level input curre	IN = 0 V		-10			μA
CMTI	Common-mode transient immunity	V_I = V_CC or 0 V; see Figure 14		25	50		kV/μs
SUPPLY CURRENT(All inputs switching with square wave clock signal for dynamic I_CC measurement)
ISO7330
I_CC1	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V		0.3	0.6	mA
I_CC2		Disable	V_I = V_CC or 0 V, EN = 0 V		0.3	0.6
I_CC1		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		0.3	0.6
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		2	3.1
I_CC1		10 Mbps	C_L = 15pF		0.7	1.1
I_CC2		10 Mbps	C_L = 15pF		3.1	4.3
I_CC1		25 Mbps	C_L = 15pF		1.2	2
I_CC2		25 Mbps	C_L = 15pF		4.8	6.3
ISO7331
I_CC1	Supply current for V_CC1 and V_CC2	Disable	V_I = V_CC or 0 V, EN = 0 V		0.5	0.9	mA
I_CC2		Disable	V_I = V_CC or 0 V, EN = 0 V		0.5	0.8
I_CC1		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		1.3	2.1
I_CC2		DC to 1 Mbps	DC Input: V_I = V_CC or 0 V, AC Input: C_L = 15pF		1.7	2.6
I_CC1		10 Mbps	C_L = 15pF		1.9	2.7
I_CC2		10 Mbps	C_L = 15pF		2.6	3.5
I_CC1		25 Mbps	C_L = 15pF		2.9	4.2
I_CC2		25 Mbps	C_L = 15pF		3.9	5.2

(1) V_CCO is supply voltage, V_CC1 or V_CC2, for the output channel being measured.

6.7 Switching Characteristics

V_CC1 and V_CC2 at 5 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 11	20	32	58	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 11			4	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Same direction channels			2.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Opposite direction channels			17	ns
t_sk(pp)⁽³⁾	Part-to-part skew time					23	ns
t_r	Output signal rise time		See Figure 11		3		ns
t_f	Output signal fall time		See Figure 11		2		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 12		7	12	ns
t_PLZ	Disable propagation delay, low-to-high impedance output				7	12
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xC			7	12
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xFC			11000	23000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xC			11000	23000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xFC			7	12
t_fs	Fail-safe output delay time from input power loss		See Figure 13		7		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(3) t_sk(pp) is the magnitude of the difference in propagation delay times between any terminals of different devices switching in the same direction while operating at identical supply voltages, temperature, input signals and loads.

(4) The enable signal rate should be ≤ 43 Kbps

6.8 Switching Characteristics

V_CC1 and V_CC2 at 3.3 V ± 10% (over recommended operating conditions unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
t_PLH, t_PHL	Propagation delay time		See Figure 11	22	36	66	ns
PWD⁽¹⁾	Pulse width distortion \|t_PHL – t_PLH\|		See Figure 11			2.5	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Same direction channels			3	ns
t_sk(o)⁽²⁾	Channel-to-channel output skew time		Opposite direction channels			16	ns
t_sk(pp)⁽³⁾	Part-to-part skew time					27	ns
t_r	Output signal rise time		See Figure 11		3		ns
t_f	Output signal fall time		See Figure 11		2		ns
t_PHZ	Disable propagation delay, high-to-high impedance output		See Figure 12		9	18	ns
t_PLZ	Disable propagation delay, low-to-high impedance output				9	18
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xC			9	18
t_PZH	Enable propagation delay, high impedance-to-high output	ISO733xFC			13000	24000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xC			13000	24000⁽⁴⁾
t_PZL	Enable propagation delay, high impedance-to-low output	ISO733xFC			9	18
t_fs	Fail-safe output delay time from input power loss		See Figure 13		7		μs

(1) Also known as pulse skew.

(2) t_sk(o) is the skew between outputs of a single device with all driving inputs connected together and the outputs switching in the same direction while driving identical loads.

(4) The enable signal rate should be ≤ 41 Kbps